03-12-2018 07:39 AM
We are using the the ZCU102 boards to build a multi-antenna digital front end (DFE) using the PC-CFR (v6.1) and DPD (v8.1) IP cores. We tried to use as a basis the reference design that comes with the DPD IP core. We want to use custom waveforms (LTE-like and 5G-like). However, it seems to us that this reference design is thought to be used i) with he XRF2 board, ii) with standard waveforms (e.g., LTE FDD) and mainly iii) programmed through the PS from an application that we don't have the source code and thus we can't customize. For instance, if we want to change the CP filters coefficients in the PC-CFR core of this reference design, this is not possible since these filters coefficients are loaded from the PS application for which we don't dispose the source code. With PS application we refer to the following SW deliverables:
- zcu102_plnx_dpd_smp_maxcpus_2017_2.bsp (to build Linux)
We also tried to build a simple HDL design with the DPD IP (without using the reference design) and the dpd_smp application crashes during Linux boot process. Probably dpd_smp is missing some memory mapped blocks in HDL design while trying to configure them.
If our assumptions hold true, would it be possible to provide us with a version of the dpd_smp application that only manages the DPD IP itself?
03-16-2018 01:54 AM
03-16-2018 04:27 AM
We are using the required versions of the tools (Vivado and Matlab) and also the latest version of the IPs (PC-CFR and DPD).
We want to modify the DPD reference design. In order to do so, we first tried to be sure that the native version (delivered as part of the DPD IP) works as expected (i.e., as it is the case with the precompiled bitstream of the debug interface for the ZCU102 board). So we produced the bitsream from the Vivado project of the DPD reference design and invoked the debug interface from Matlab to program the device with the default programming options, using the software deliverables of the DPD reference design (i.e., - dpd_smp + zcu102_plnx_dpd_smp_maxcpus_2017_2.bsp). The error message that we get in Matlab is the following:
Error using axi_readburst
axi_readburst: Memory read error at 0xAC008000. AXI AP transaction error, DAP status 30000021
Error in axi_readburst
Error in hw_regs/read_burst
Error in hw_regs/read_regs
Error in hw_dfe_rom/get_dfe_parameters
Error in hw_dfe_rom/get_rom_config
Error in initialize_system
Error in config_image
Error in jtag_init
Error in jtag_init
Error while evaluating UIControl Callback
We also tried to instantiate the DPD IP core (from scratch), copying in a certain extent the clocking modules of the DPD reference design, but again without any luck (the dpd_smp application crashes). I don't have the log from this test but I can reproduce it if it would be necessary.
Thanks a lot in advance.
03-26-2018 04:27 AM
As DPD reference design we refer to the "DFE subsystem reference design v2.1" which we have downloaded from the DPD IP evaluation lounge.
We haven't been able to find a way to use the Xilinx DPD IP core for almost the past two months.
It seems to us that we need to have the right dpd_smp application "talking" to the PL part of the DPD IP core.
Could you please provide us with a Vivado project that instantiates the DPD IP core and is able to work flawlessly with the SW part of the IP core (dpd_smp) AND can also be generic enough to be customized according to our project specifications without breaking the communication between the PS part of the DPD with that residing in the PL?
We can't really proceed to buy the DPD IP, (in fact our system will involve a number of licenses for the DPD, PC-CFR and CPRI cores) if we cannot priory evaluate it with the specific requirements of our project.
Thank you very much in advance.
09-07-2019 09:45 AM
09-07-2019 12:11 PM
At that time (mid 2018), we did make some advances and we managed to communicate with the DPD application, but without managing to get the DPD reference design working. Some debugging steps were assumed to be obvious or generic (and thus were not included) in the PG076 and UG989 (we also had similar problems with the PetaLinux related UGs). I guess that the Xilinx author(s) of these 2 docs believed that we should be aware of that information. However,it wouldn't have been a big deal to include some additional steps or add some pointers to other Xilinx documentation. We made questions to our local FAE, but he was just forwarding them directly to the US team (we got some partial answers to our questions, but this was too little too late).
Eventually, to answer your question, we lost a lot of valuable time only to abandon our idea of using the Xilinx DPD IP core. We designed our own simple DPD (open loop, with ability to be reconfigured with different coefficient that were calculated offline).
09-07-2019 06:07 PM
Thank you for the reply. Your answer was descriptive and useful.
My concern is xilinx haven't shared the sample test case scenario to check DPD IP (one test case is enough to compare it with standard results) . I raised the service portal request for this but you already worked on this so asked this question here.
I don't know yet how to test the IP in MATLAB debug interface. There are no standard configuration parameters. If we don't have the standard test case scenario how can we test customised test cases.
Sorry for posting the queries in your thread but it was urgent.