06-05-2014 06:14 AM
I am sending DDS output to the input of DP RAM when the WE of DPRAM is high and taking the outputs when my RDEN is high.
But some of the outputs of DPRAM are missing,They are different from the input values.
What can be the reason??
06-05-2014 06:43 AM
06-05-2014 07:03 AM
I havent crossed the data with respect to write and read address.
I am writing dds(7 downto 0) at the memory when the tvalid_dds is high and I am reading the same thing when the data_tready of my fft is high.
I am using simple dual port RAM for virtex-6.I am not using any ip core to generate DP Ram.
06-05-2014 07:09 AM
you must need to verify the data with respect to address location. Please make sure all the control signal asserted correctly as defined in product guide
06-05-2014 09:08 PM
What are the clocks used for DDS and the DPRAM.
Check if any collisions are happening.
Refer below doc for the collision behaviour
06-09-2014 10:00 PM
Can you attach the simulation dump to debug the issue further.