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sourav_poddar
Visitor
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8,933 Views
Registered: ‎05-20-2014

DPRAM ISSUE

I am sending DDS output to the input of DP RAM when the WE of DPRAM is high and taking the outputs when my RDEN is high.
But some of the outputs of DPRAM are missing,They are different from the input values.
What can be the reason??

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balkris
Xilinx Employee
Xilinx Employee
8,930 Views
Registered: ‎08-01-2008

i think first you need verify the functionality of DPRAM.

Have you cross the data with respect to write and read address.

Can you please show me what you written in memory and what you reading from read port .

Please confirm if you are using Block Memory Generator core or BRAM primitive
Thanks and Regards
Balkrishan
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sourav_poddar
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Registered: ‎05-20-2014

I havent crossed the data with respect to write and read address.
I am writing dds(7 downto 0) at the memory when the tvalid_dds is high and I am reading the same thing when the data_tready of my fft is high.
I am using simple dual port RAM for virtex-6.I am not using any ip core to generate DP Ram.

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

you must need to verify the data with respect to address location. Please make sure all the control signal asserted correctly as defined in product guide

Thanks and Regards
Balkrishan
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yenigal
Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

What are the clocks used for DDS and the DPRAM.

 

Check if any collisions are happening.

 

Refer below doc for the collision behaviour

 

http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen_ds512.pdf

Regards,

Satish

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sourav_poddar
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Registered: ‎05-20-2014

I am multiplying my DDS input at 16 MHZ to PN sequence at 64 MHz.Then sending the output through DPRAM at 64 MHz

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yenigal
Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

Can you attach the simulation dump to debug the issue further.

Regards,

Satish

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