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Observer
Observer
236 Views
Registered: ‎10-08-2012

DSP adder architecture

Hello,

for some scientific purpose I have investigated delays in a DSP slice adder (Spartan-6). I set one input (C) to logic ones and the other one (D:B:A) connected to a signal in one-hot code. Then I observed how much time does it take to see changes on CARRYOUTF output (carry propagation). Attached file presents results obtained in 16 DSPs (grey lines) and mean value (red line). The delays have been shown relative to the last setting (48: X "8000_0000_0000").

I wonder what kind of adder is implemented in the DSP slice? Is it possible to find somewhere such information? What is the reason for such different delays at the beginning (steps 1-12). Is it the same adder structure in Series-7, Ultrascale and Ultrascale (I know that there is ALU instead of adder) ?

CARRYOUTF delay.jpg
1 Reply
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Adventurer
Adventurer
227 Views
Registered: ‎05-19-2014

Very interesting work! Since it is a hard-wired adder, you can assume that they will invest in an advanced fast adder with logarithmic delay. Given the four inputs (the multiplier contributes two after matrix reduction), the first stage is certainly a constant-time 4:2 adder followed by some form of parallel prefix adder, carry-lookahead adder, conditional sum adder, ... It would be nice to hear what hypothesis will turn out to explain your observations.