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394 Views
Registered: ‎08-05-2019

DSP48E1 48 bit (A:B + C) addition: Output P is always zero.

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I am trying to use the DSP48E1 slice to add 2 48-bit numbers. However the output P from behavioral simulation on Vivado 2019.1 is always zero even with different settings. 

My ALUmode, Opcode, Inmode are as follows:

ALUMode = 4'b0000; (Z+X+Y+CIN)
InMode = 5'b00000; 
OpMode = 7'b0001111; (Z=0 , X = A:B, Y = C)

I have attached my dsp slice instantiation and testbench files too.

Can someone help me with this? This is the main building block for my project and I can't proceed further without it. Stuck on this since 2 days. Thanks in advance.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2019

Re: DSP48E1 48 bit (A:B + C) addition: Output P is always zero.

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Hello @pragpatel1998 

There are a few things that need to be changed in the dsp_module.v file in order to make the DSP slice work, but you got the main idea of how the DSP is configured! 

1) Change ".USE_MULT" argument from "MULTIPLY" to "NONE".

2) Change ".MREG" argument from 1 to 0 because you are not using the multiplier. 

3) In the language template of the DSP48E1, it says to connect all inputs and outputs, so that must be done. 

4) For your specific application, because you're not streaming data continuously to the DSP slice, make all of the pipeline stages 0. This will make your waveform cleaner looking.

I will attach your code that I have edited, so that you can see all the changes I have made. I hope you have found this helpful and I wish you luck in your project! 

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1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎07-11-2019

Re: DSP48E1 48 bit (A:B + C) addition: Output P is always zero.

Jump to solution

Hello @pragpatel1998 

There are a few things that need to be changed in the dsp_module.v file in order to make the DSP slice work, but you got the main idea of how the DSP is configured! 

1) Change ".USE_MULT" argument from "MULTIPLY" to "NONE".

2) Change ".MREG" argument from 1 to 0 because you are not using the multiplier. 

3) In the language template of the DSP48E1, it says to connect all inputs and outputs, so that must be done. 

4) For your specific application, because you're not streaming data continuously to the DSP slice, make all of the pipeline stages 0. This will make your waveform cleaner looking.

I will attach your code that I have edited, so that you can see all the changes I have made. I hope you have found this helpful and I wish you luck in your project! 

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------