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Observer
Observer
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Registered: ‎01-08-2018

DSP48E1 combinatorial delay

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I am playing with FPGAs for some number crunching. Those days I am looking at DSP primitive. I've used some already but yesterday I tried something different by having them combinatorial. I am using SystemVerilog in Vivado 2017.4.

 

What I have done is f(a, b, c) = a xor (b op c), where op can be selected by an input. When op=1 I do a xor (b or c), otherwise I do a xor (b and c).

 

I attach the module file below for those intersted but it's fairly standard learning thing.

 

Now, I have observed I have very low delay from the operations. Considering typical latency in (discrete!) AND, OR, XOR gates I still ok, but when I added the cascaded dsp, the latency did not appear to change.

 

So basically, once I fetch my values to the areg, breg, cregs they get almost instantly to pcout and then instantly to another dsp and to its p.

 

Now, in the module I made a thing to check this out: since I mangle 64 bit values I must use two tiles of DSPs, I have instantiated one without a P reg. Indeed, the value appears (in simulation) at p with no delay, whereas the dsp equipped with the final p-reg have an extra delay of latency.

 

It looks like this:

 

dsp-comb-delay.gif

 

 

 

 

 

 

 

 

 

 

 

 

At 2900 ns I set the registers driving my wires to the dsp module. 1 clock later the low bits (which do not have a p-reg) are already out.

 

Is it... well, real? Logic gates are fast, even when discrete components and using the cascaded wires I assume the only propagation delay is electricity itself but shouldn't there be at least some delay? Perhaps this only holds for logic ops?

 

I have another question.

 

My understanding was using the input regs (areg, breg, creg) and the output reg (preg) helps place and route as it somehow allows less stringent timings. How is that the case? In the waves above, the timing from low-bits-out to next clock seem to be the same as high-bits-out to next.

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Highlighted
1,036 Views
Registered: ‎06-21-2017

Re: DSP48E1 combinatorial delay

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Is this only a behavioral simulation?  There are no clock-to-out delays in most Xilinx models, except possibly some critical I/O related ones.  If you want to see real timing, do a post place & route simulation.

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Highlighted
1,037 Views
Registered: ‎06-21-2017

Re: DSP48E1 combinatorial delay

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Is this only a behavioral simulation?  There are no clock-to-out delays in most Xilinx models, except possibly some critical I/O related ones.  If you want to see real timing, do a post place & route simulation.

View solution in original post

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Observer
Observer
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Registered: ‎01-08-2018

Re: DSP48E1 combinatorial delay

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Ew! I noticed the arcs annotations were nonsensical as well. Too good to be true! Will do; thank you!
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