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Visitor boothby
Registered: ‎06-17-2019

DSP48E1 comparator timing

I've been reading over this forum, DS183 and UG479 and haven't found an answer to the following...

I'm attempting to use a DSP48E1 as an "a<b" comparator.  My application calls for a boatload of comparators running simultaneously; roughly speaking, each comparator is responsible for finding the minimum of a stream* of values.  The common advice I see in the forum is to use the deepest pipeline possible to maximize the operating frequency.

The resulting latency does not come "free," as I see claimed in several answers, since the inputs of each comparison depends on the last (and I can't accumulate the minimum into P). So my question is: if I'm not using the multiplier or the pattern detector, what's the maximum frequency I can get away with?  Additionally, do I need "all" registers to attain that performance, or can I skip some?  I'm using a xc7vx690t-2.

* my actual application is more complex than just streams of data, so splitting them and taking a minimum at the end is less efficient than I'd like

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Registered: ‎08-01-2007

回复: DSP48E1 comparator timing

DSP48E1 hard back has a set internal registers, if none of the internal registers are set, the DSP48E1 operates as a combinatorial logic, and it will have a long delay, so DSP48E1 runs at slower clock rate if NO register is configured. 

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