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matst
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Visitor
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Registered: ‎01-11-2019

DSP48E2 MACC_EXTEND

Hi!

I am using multiply accumulate on a RFSoC and need more than 48-bit sum. Using MACC_EXTEND to get a 96-bit sum i get different behaviour in simulation and in the synthesized design. The simulation model does not seem to work, the synthesized design seems to work but i have yet not been able to figure out how to reset the extension DSP in a continous stream of data where output in one clock cycle is an accumulated sum and the next cycle the output depend only on the sign of the multiply. In the "primary" DSP this functionality is implemented by changing the opcode from "multiply accumulate" to "multiply" to restart the accumulator.

 

Any help or information about how to solve these problems are appreciated.

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @matst ,

The difference in simulation and synthesis is expected when DSP cascade model is used. This is mentioned in the UG579, page 70-72 which talks about the Cascading DSP slice case and explanation of the difference in synthesis and Simulation.

As for your other question can you please elaborate more on the requirement .

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matst
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Registered: ‎01-11-2019

Hi!

Thanks for looking into my problem!

DSP48E2 MACC_EXTEND generates incorrect results in my simulations, not just different internal signalling but incorrect result. Should not the simulation model at least generate the same output as the actual hardware? Am i doing something wrong or is the simulation model broken?

My requirement is that i have two continous streams of data (one pair of data every clock cycle) that i want to multiply and accumulate in a 96-bit accumulator. Periodically i want to read the accumulator, reset and start accumulating again without gap between the two sums. All input data must part of one sum.

 

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vkanchan
Xilinx Employee
Xilinx Employee
516 Views
Registered: ‎09-18-2018

Hi @matst ,

Can you provide me with a testbench for me to check this ? 

 

Regards,

Vivek

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