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Visitor
Visitor
1,202 Views
Registered: ‎06-05-2018

DSP48E2 PREG warning

Hi

 

I have a problem with DSP48E2. I'm getting this warning during the implementation:

DPOP #1 DSP i_0_FIR/i_16_DSP48E2/DSP48E2_I output i_0_FIR/i_16_DSP48E2/DSP48E2_I/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 

 

I need to improve timing because rigth now I have problems with worst negative slack.

 

following is the part of the code for the reference.

 

DSP48E2_I : DSP48E2
generic map (
-- Feature Control Attributes: Data Path Selection
AMULTSEL => "AD", -- Selects A input to multiplier (A, AD)
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
BMULTSEL => "B", -- Selects B input to multiplier (AD, B)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
PREADDINSEL => "A", -- Selects input to pre-adder (A, B)
RND => X"000000000000", -- Rounding Constant
USE_MULT => "MULTIPLY", -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
USE_SIMD => "ONE48", -- SIMD selection (FOUR12, ONE48, TWO24)
USE_WIDEXOR => "FALSE", -- Use the Wide XOR function (FALSE, TRUE)
XORSIMD => "XOR24_48_96", -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96)
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH
AUTORESET_PRIORITY => "CEP", -- Priority of AUTORESET vs. CEP (CEP, RESET).
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
SEL_PATTERN => "PATTERN", -- Select pattern value (C, PATTERN)
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect (NO_PATDET, PATDET)
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
IS_ALUMODE_INVERTED => "0000", -- Optional inversion for ALUMODE
IS_CARRYIN_INVERTED => '0', -- Optional inversion for CARRYIN
IS_CLK_INVERTED => '0', -- Optional inversion for CLK
IS_INMODE_INVERTED => "00000", -- Optional inversion for INMODE
IS_OPMODE_INVERTED => "000000000", -- Optional inversion for OPMODE
IS_RSTALLCARRYIN_INVERTED => '0', -- Optional inversion for RSTALLCARRYIN
IS_RSTALUMODE_INVERTED => '0', -- Optional inversion for RSTALUMODE
IS_RSTA_INVERTED => '0', -- Optional inversion for RSTA
IS_RSTB_INVERTED => '0', -- Optional inversion for RSTB
IS_RSTCTRL_INVERTED => '0', -- Optional inversion for RSTCTRL
IS_RSTC_INVERTED => '0', -- Optional inversion for RSTC
IS_RSTD_INVERTED => '0', -- Optional inversion for RSTD
IS_RSTINMODE_INVERTED => '0', -- Optional inversion for RSTINMODE
IS_RSTM_INVERTED => '0', -- Optional inversion for RSTM
IS_RSTP_INVERTED => '0', -- Optional inversion for RSTP
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0-2)
ADREG => 1, -- Pipeline stages for pre-adder (0-1)
ALUMODEREG => 0, -- Pipeline stages for ALUMODE (0-1)
AREG => 1, -- Pipeline stages for A (0-2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0-2)
BREG => 1, -- Pipeline stages for B (0-2)
CARRYINREG => 0, -- Pipeline stages for CARRYIN (0-1)
CARRYINSELREG => 0, -- Pipeline stages for CARRYINSEL (0-1)
CREG => 1, -- Pipeline stages for C (0-1)
DREG => 1, -- Pipeline stages for D (0-1)
INMODEREG => 0, -- Pipeline stages for INMODE (0-1)
MREG => 1, -- Multiplier pipeline stages (0-1)
PREG => 1, -- Number of pipeline stages for P (0-1)
OPMODEREG => 0 -- Pipeline stages for OPMODE (0-1)
)
port map (
-- Cascade outputs: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade
BCOUT => open, -- 18-bit output: B cascade
CARRYCASCOUT => open, -- 1-bit output: Cascade carry
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade
PCOUT => PC_O, -- 48-bit output: Cascade output
-- Control outputs: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect
PATTERNDETECT => open, -- 1-bit output: Pattern detect
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc
-- Data outputs: Data Ports
CARRYOUT => open, -- 4-bit output: Carry
P => P_O, -- 48-bit output: Primary data
XOROUT => open, -- 8-bit output: XOR data
-- Cascade inputs: Cascade Ports
ACIN => acin, -- 30-bit input: A cascade data
BCIN => bcin, -- 18-bit input: B cascade
CARRYCASCIN => ZERO, -- 1-bit input: Cascade carry
MULTSIGNIN => ZERO, -- 1-bit input: Multiplier sign cascade
PCIN => PC_I, -- 48-bit input: P cascade
-- Control inputs: Control Inputs/Status Bits
ALUMODE => AL_M, -- 4-bit input: ALU control
CARRYINSEL => ZERO3, -- 3-bit input: Carry select
CLK => CLK, -- 1-bit input: Clock
INMODE => IN_M, -- 5-bit input: INMODE control
OPMODE => OP_M, -- 9-bit input: Operation mode
-- Data inputs: Data Ports
A => ai, -- 30-bit input: A data
B => bi, -- 18-bit input: B data
C => ci, -- 48-bit input: C data
CARRYIN => ZERO, -- 1-bit input: Carry-in
D => di, -- 27-bit input: D data
-- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
CEA1 => ONE, -- 1-bit input: Clock enable for 1st stage AREG
CEA2 => ONE, -- 1-bit input: Clock enable for 2nd stage AREG
CEAD => ONE, -- 1-bit input: Clock enable for ADREG
CEALUMODE => ZERO, -- 1-bit input: Clock enable for ALUMODE
CEB1 => ONE, -- 1-bit input: Clock enable for 1st stage BREG
CEB2 => ONE, -- 1-bit input: Clock enable for 2nd stage BREG
CEC => ZERO, -- 1-bit input: Clock enable for CREG
CECARRYIN => ZERO, -- 1-bit input: Clock enable for CARRYINREG
CECTRL => ZERO, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
CED => ONE, -- 1-bit input: Clock enable for DREG
CEINMODE => ZERO, -- 1-bit input: Clock enable for INMODEREG
CEM => ONE, -- 1-bit input: Clock enable for MREG
CEP => ONE, -- 1-bit input: Clock enable for PREG
RSTA => ZERO, -- 1-bit input: Reset for AREG
RSTALLCARRYIN => ZERO, -- 1-bit input: Reset for CARRYINREG
RSTALUMODE => ZERO, -- 1-bit input: Reset for ALUMODEREG
RSTB => ZERO, -- 1-bit input: Reset for BREG
RSTC => ZERO, -- 1-bit input: Reset for CREG
RSTCTRL => ZERO, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG
RSTD => ZERO, -- 1-bit input: Reset for DREG and ADREG
RSTINMODE => ZERO, -- 1-bit input: Reset for INMODEREG
RSTM => ZERO, -- 1-bit input: Reset for MREG
RSTP => ZERO -- 1-bit input: Reset for PREG
);

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Xilinx Employee
Xilinx Employee
1,174 Views
Registered: ‎08-02-2011

Re: DSP48E2 PREG warning

This code must not match the specific DSP slice that the message is complaining about because it has PREG set to 1.

Can you post your schematic showing the DSP slice in question's properties and the snippet of the timing report showing the failing path?
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Visitor
Visitor
1,147 Views
Registered: ‎06-05-2018

Re: DSP48E2 PREG warning

 I attach the timing report and the schematic of Path 1

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Xilinx Employee
Xilinx Employee
1,142 Views
Registered: ‎08-02-2011

Re: DSP48E2 PREG warning

Hello,

 

Thanks for the info, but i'll need just a little more detail: in the timing report, double-click the path to bring up the detailed view and post that. Or the text version if you prefer.

 

Anyway, there are some odd things in the schematic:

- You have some blocks labeled i_28_DSP48E2, which I assume is a wrapper around your DSP primitive instantiation. However, there are some LUTs in there which is surprising.

- I was hoping to see the actual DSP slice primitive in the schematic along with it's 'Properties' window to confirm if PREG is indeed being used.

- I see some carry chains outside the DSPs... did you intend to have fabric adders for your FIR?

- Is there a reason you're not using the FIR Compiler IP block?

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