DSP48E2 in ZYNC - How can I use SIMD modes

[lior.mor]

Hi.

I want to define\instance DSP48 IP with the CONCAT functions, as described in ug579 pdf file, pages 31-37 and so.

Using the IP catalog in VIVADO, I can't find how to define my use as SIMD mode or ALUMODE..

My purpose is to use a single DSP48E2 slice, in ZYNC Ultrascale+ (xczu19eg-ffve1924), as an adders unit:

2 inputs of 24bit (single adder for 24+24)

or 4 inputs of 12bit (and have here two adders of 12+12).

HOW do i need to do it?

Thanks in advance,

Lior.

[lior.mor]

Anyone, please?

[bruce_karaffa]

If you really want to do this, you will probably need to instantiate the DSP48 primitive in RTL (VHDL or Verilog) and set the ALUMODE and OPMODE in your code.  The larger question is why?  Is your device so full that you can't just let the synthesis tool do the additions in fabric? 

[lior.mor]

Thank you.

I want to have many units off DPS48E2 slices as adders. If I let the tool does it autonomous, the FPGA may be too full to work..

I want to use every DSP48e2 slice as an adder with two 24bit inputs.

I didn't find the way to set it via the IP catalog in VIvado.

The better solution can be if it's possible to make it configurable (and not before synthesis) to change between two inputs of 24 bit to 4 input of 12 bit.

Thanks.

[bruce_karaffa · Accepted solution]

As I said, if you instantiate the DSP slices and write code to control the OPMODE and ALUMODE, you should be able to switch between adder modes.  You will probably need to multiplex the inputs to the DSP, between 12 bit and 24 bit data.  That will take up nearly as much logic as the adders. You might make use of the Input A/ Input D multiplexer to reduce the amount of logic and Mux/CARRY resources you need and get some savings there.  It's almost impossible to use every DSP slice, but you should be able to use most of them. 

A word of advice, this kind of code is hard to maintain.  Write lots of comments.  Keep the comments up to date.  Store your timing/state diagrams in your project folder.