06-19-2020 06:48 AM
I am trying to understand some basics in DFE. I am using zcu111 . In http://read.pudn.com/downloads160/doc/718492/LTE%20DFE%20App%20Note.pdf it is referred that FPGA clock Rate is 368.64 MHz ( I assume that this equals to the AXI4 -stream clock of RFDC IP in my situation).
1 ) how does the system goes from 122.88Msps to 368.64MHz (Should i just have axi stream clock 368.64MHz in my DFE to match to the example? ) ? Is there any extra interpolation needed?
2) Which is the criteria for the x3 in FPGA clock Rate?
Sorry if my question is silly. Still trying to understand some things.
Thanks in Advance,
06-19-2020 08:57 AM
I don't know for sure the answer to your question, but I would suggest checking if that IP is instantiating an MMCM. You could check this by reporting utilization on the implemented design, it shows utilization per IP.