We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer alexdetrano
Registered: ‎06-02-2009

Data Manipulation using RAM block



I am trying to rearrange some data using RAM blocks and such.   I am trying to take a stream of data such as <d1 d2....d11457> and rearrange that into 3 streams of data.  However, they need to be in a certain order.  Such as:


<d1 d604 d1207...>

<d2 d605 d1208...>

<d3 d606 d1209...>


Concerning only the first stream:


I have tried to do this by using a single port RAM block.  I have the data going into the 'data' port.  Into the 'address' port I have a ROM block which has been initialized to a vector of [1  604 1207...11455].  The ROM block is attached to a free running counter.    The 'we' block is attached to a relational block, which has the counter being compared to a value of 3820 (the amount of DATA that I want to read out of RAM).  


On my output, I get the correct adddress locations, but the data doesn't show up.


Does anybody know how I can achieve this?  When I look at the output in MATLAB, I see the address locations in the right order, and after 3819 values, the output just holds the final value.  I want this to go to zero (as I will be applying a filter to it later). 


I have attached my model thus far. 


For data, I have been doing rand(1,11457)


Any help would be GREATLY appreciated! 

Tags (1)
0 Kudos