UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
280 Views
Registered: ‎05-13-2018

Data-Width Conversion in FIFO Generator simulink and dspgen

Hello all,

I am using Matlab simulink and Xilinx sysgen. In this I would like to impleament a FIFO with input port data type depth and width of 2048 X 32 and output port data type 1024 X 64. Basically looking a similar module like this https://www.xilinx.com/support/documentation/application_notes/xapp261.pdf .  or how to implement / configure  Data-Width Conversion on a FIFO for a virtex 5 chip. 

Thanks 

indrajit 

 

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎09-18-2018

Re: Data-Width Conversion in FIFO Generator simulink and dspgen

Hi @indrajitbarve ,

The FIFO block in the Sysgen doesnot provide the facility to use data width conversion on the FIFO I/O ports. 

A way would be to use custom design FIFO in HDL and import that into the Sysgen.

0 Kudos
217 Views
Registered: ‎05-13-2018

Re: Data-Width Conversion in FIFO Generator simulink and dspgen

Thanks, for your reply.

0 Kudos