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Observer vghs1988
Observer
6,391 Views
Registered: ‎04-29-2016

Different sysgen Output after generating Hardware co simulation model

Hello to xilinx experts. I made a simple system generator model that produces a pulse. The model blocks are as following picture:

 

Untitled.png

here is the output on system generator scope:

 

Untitled1.png

 

After I generate the Hardware Co simulation model and program it on my FPGA board, the FPGA output is as expected.

But when I connect a scope to see the output of Hardware Co simulation block, it is not the same as the top figure.

 

Here is a snapshot of Hardware Co simulation and output of it:

 

Untitled3.png

Untitled4.png

 

would you please help me why there is difference between these two outputs?

 

If a parameter must be known to guide me, let me know to tell you.

 

Regards

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19 Replies
Observer vghs1988
Observer
6,348 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Is it possible for you to help me? It is really urgent.

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Observer vghs1988
Observer
6,269 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

I have encountered to a big problem and had no success in solving it. would you please help me? 

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Adventurer
Adventurer
6,266 Views
Registered: ‎02-23-2013

Re: Different sysgen Output after generating Hardware co simulation model

Please use model with Hawdware cosim together to see if it works as expected.

 

Model block + Hardware Cosim block to one scope with two ports.

 

The waveform is different ?

 

debugasm

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Observer vghs1988
Observer
6,252 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Hello, thanks for your reply friend.

 

 

The problem that I encountered is that when I put the clocking mode of Hardware co sim block on free running, I have the correct output on FPGA board, but I get different waveforms on the scope connected to hardware co sim block & on the scope connected to model block.

 

when I put the clocking mode of Hardware co sim block on single stepped, I get nothing on FPGA board, but this time I get similar outputs on scopes connected to hardware co sim and model block.

 

Would you please help me about this.

 

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Xilinx Employee
Xilinx Employee
6,209 Views
Registered: ‎05-07-2015

Re: Different sysgen Output after generating Hardware co simulation model

HI @vghs1988

 

I tried some on similar lines, things seem fine. Can you please share your sysgen model (.slx) here?

Thanks
Bharath
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Observer vghs1988
Observer
6,200 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Thanks for your reply friend.

 

I attached the model block.

 

You can generate a hardware co sim model from the attached model and download it on a FPGA board.

 

you can define a New Compilation Target by double clicking System Generator token (red cross shaped block) and define a output pin.

 

If you need to know any other information, let me know

 

 

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Observer vghs1988
Observer
6,128 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

this problem has suspended my progress for a couple of days. I really need your help.

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Xilinx Employee
Xilinx Employee
6,114 Views
Registered: ‎05-07-2015

Re: Different sysgen Output after generating Hardware co simulation model

Hi @vghs1988

 


In free-running mode, you must build explicit synchronization mechanisms into the System Generator model. A simple example is a status register, exposed as an output port on the hardware co-simulation block, which is set in hardware when a condition is met. The rest of the System Generator model can poll the status register to determine the state of the hardware.

"In free-running clock mode, the hardware runs asynchronously relative to the software simulation. Unlike the single-step clock mode, where Simulink effectively generates the FPGA clock, in free-running mode, the hardware clock runs continuously inside the FPGA itself. In this mode, simulation is not bit and cycle true to the original model, because Simulink is only sampling the internal state of the hardware at the times when Simulink awakes the hardware co-simulation block. The FPGA port I/O is no longer synchronized with events in Simulink. When an event occurs on a Simulink port, the value is either read from or written to the corresponding port in hardware at that time. However, since an unknown number of clock cycles have elapsed in hardware between port events, the current state of the hardware cannot be reconciled to the original System Generator model." ref: UG897

Thanks
Bharath
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Observer vghs1988
Observer
6,054 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

@nagabhar Thanks for your description dear friend.

 

The question that I wondering is that, why I have no output on FPGA board in single stepped mode, but I have the correct output on free running mode? 

 

What is wrong with my model that I attached?

 

Regards

 

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Observer vghs1988
Observer
6,136 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

I am really confused, would you please give a solution after looking at slx model file?

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Observer vghs1988
Observer
6,052 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Hello. 

 

I really need this problem to be solved. because this is the priniciple of my work.

 

I will appreciate any help

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Advisor eilert
Advisor
5,957 Views
Registered: ‎08-14-2007

Re: Different sysgen Output after generating Hardware co simulation model

Hi, nagabhar already pointed to the right solution. But let me put it in different words. There are single step and free running mode for HW-Cosimulation. One is to test DSP-cores WITHOUT driving any real output pins. That's because the simulator and the cores need to synchronize each step, which can take a long time (compared to the clock cycle) e.g: while your FPGA Clock works at 100 MHz the JTAG uses just about 1 MHz and during the time the host communicates with the FPGA the DSP-core is kept on hold, so would be the outputs, which makes it impossible to properly drive any interface. The other is to supervise and configure DSP-cores while they are working. e.g. if you have some 32 line sound equalizer connected to some AC97 soundchip. Then you can feed in some music and hear how the equalizer affect the spectrum of the sound. You may have provided some registers that allow setting the gains for each frequency line . Or some registers to read out the median and peak sound levels (VU-meter) . That can happen quite slowly over the JTAG interface, without disrupting the equalizer. So each mode has its special use and drawbacks. (Very well described in the DSP-Generator documentation!) In your case, the free running mode creates a nice signal on the FPGA output, but the host takes samples of that signal at random times, showing some funny result. And, as you already experienced, in single step mode, everything looks fine for the host, only that there's no signal available at the FPGA pins. That's just how things work. Have a nice synthesis Eilert
Xilinx Employee
Xilinx Employee
5,953 Views
Registered: ‎05-07-2015

Re: Different sysgen Output after generating Hardware co simulation model

@vghs1988

 

sorry , I did not see your subsequent posts on this thread.
Thanks @eilert for explaining.

To summarize,
If you want to test the design on board , use freerunning mode.
If you want to compare the functional equivalency of HW model with that of the simulink model, use single-step mode.

As mentioned before, in freerunning mode:  if you want to capture HW cosim output in simulink ,  you must build explicit synchronization mechanisms into the System Generator model.
ref page 132 of UG897 for more clarity on this. It is well explained in the document.

 

Thanks
Bharath
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Observer vghs1988
Observer
5,937 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Mr @eilert thank you very much for your detailed replay. Mr @nagabhar thank you for your comments

 

In fact I am implementing a simple A/D converter with system generator and my FPGA board, I was interested in comparing the scope wave forms on my A/D output to waveforms of A/D in system generator, which as you said, seems impossible to simultainously watch at compare. Am I right?

 

Best Regards 

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Observer vghs1988
Observer
5,931 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Mr @nagabhar would you please guide me about making "explicit synchronisation" for the model that I attached?

 

Best regards

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Observer vghs1988
Observer
5,895 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Mr @eilert & Mr @nagabhar would you please help me about using a read & write memory to do explicit synchronisation between sysgen & FPGA board?

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Observer vghs1988
Observer
5,839 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Is it possible to implement a Real-Time Signal Processing using Hardware Co-Simulation for the model that I attached using JTAG? all the examples are done using Ethernet protocol.

 

I tried all the methods proposed in that section page 280 of sysgen_user, FIFOs and other types of shared memories. but none of them give me the right solution. Some of them give me a wrong wave form. I expect to see a wave form exactly the same as one on my input counter.

and others give error during simulations.

 

Please help me

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Advisor eilert
Advisor
5,813 Views
Registered: ‎08-14-2007

Re: Different sysgen Output after generating Hardware co simulation model

Hi,

I think you should drop the idea of using DSP-Generator's HW-Cosimulation features for your approach.

 

Rethink your true intentions. What are they?

 

You want to check wether a generated signal looks the same in Hardware as what you see in simulation?

Setup the Hardware and add the ChipScope blocks to verify the behavior.

 

You want to do some nice AD/DA conversion stuff and view the results on the host?

Red Pitaya might be a good choice friend. Look for it.

 

Have a nice synthesis

 

Eilert

 

 

 

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Observer vghs1988
Observer
5,805 Views
Registered: ‎04-29-2016

Re: Different sysgen Output after generating Hardware co simulation model

Hi Mr @eilert thanks for your nice guides in last 20 days.

 

I use a 8 bit TLC549 A/D converter that gives me a output on a pin. I want to see that pin the same way that I see on scope and use it for my closed loop calculations.

 

So, for the first step I tried to put a pulse on a arbitary pin on my FPGA and see wheter I can see the same wave form as what I see on scope or not (on free running mode)

 

then I encountered these problems. Even I tried chipscope, but this gives me the wrong waveform.

 

I tried share memories likeFIFOs, but they dont give a correct answer on free running mode.

 

I saw a solution that said I should write shared memories in free running mode and read them on single stepped. Do you have an Idea how this can be possible? Is there any free running or single stepped clocking block other than options on generated Hardware Co simulation block?

 

best regards

 

 

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