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Visitor xekortzio
Visitor
6,583 Views
Registered: ‎02-26-2013

Differential clock in system generator

Hi,

 

I'm trying to make a simple design in sysgen for, I only want to run a counter and get the result by leds.


I used to program VIRTEX 5 in vhdl and I always convert the differential clock input in a signal to work with,  this time I can't find the way to configure a differential clock input in sysgen.

 

thanks

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8 Replies
Adventurer
Adventurer
6,582 Views
Registered: ‎08-20-2007

Re: Differential clock in system generator

You need to instantinate a clock buffer, which converts differential signal to single-ended. I usually do it by managing project in ISE and instantinating SysGen design as a module, and clock buffer as the module too. Then I connect CLK lines of sysgen design in VHDL Top Module.

 

 

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Visitor xekortzio
Visitor
6,559 Views
Registered: ‎02-26-2013

Re: Differential clock in system generator

I know how to get a single-ended clk but I don't know how to connect the single end clk to the clk of the sysgen design.

 

Thanks

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Adventurer
Adventurer
6,557 Views
Registered: ‎08-20-2007

Re: Differential clock in system generator

 

I don't know how to connect the single end clk to the clk of the sysgen design.

You have to learn ISE a little bit. When you generate VHDL from Sysgen design then CLK port appears as input to your module.

 

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Visitor xekortzio
Visitor
6,546 Views
Registered: ‎02-26-2013

Re: Differential clock in system generator

I know that, but the problem is that if I add only the 2 VHDL files which are generated by sysgen, is not working I have errors about clk_(and a lot of numbers). If I open as a project is also possible to change it?

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Adventurer
Adventurer
6,537 Views
Registered: ‎08-20-2007

Re: Differential clock in system generator

You have to create a Top level VHDL Module, where you instantinate Sysgen and Clock buffer modules, using ther instatntination templates. Then you connect CLK lines using signals and generate constraints files.

ISE has functionality to include whole Sysgen - e.g you can open it from ISE in MATLAB.

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Visitor xekortzio
Visitor
6,529 Views
Registered: ‎02-26-2013

Re: Differential clock in system generator

I've got it! thanks!!

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6,468 Views
Registered: ‎04-22-2013

Re: Differential clock in system generator

hello xekortzio i am working on same thing but with different application, i am also facing same problem regarding feeding clock to counter, can u help me how you debug this 

thanx

aman

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6,456 Views
Registered: ‎04-22-2013

Re: Differential clock in system generator

did u get ur problem solved, i am new i dealing with this from last month and nt able to crack it 

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