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Registered: ‎06-05-2018

Differents delays in DSPs



I'm doing a FIR filter and I instance a DSP for each operation. When I simulate behavioral and post-shyntesis the filter works well. But in post place and route filter doesn't work. I've investigated the input and output signals in every DSP and I saw that in behavioral and post-synthesis a DSP has a delay of 4 cicles but in PP&R some DSPs have 3 cicles and others 4 cicles. The DSPs configuration is exactly the same.


I change the optimizations and the delays change, but the filters doesn´t work yet.


DPSs has next configuration:


-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0-2)
ADREG => 1, -- Pipeline stages for pre-adder (0-1)
ALUMODEREG => 0, -- Pipeline stages for ALUMODE (0-1)
AREG => 1, -- Pipeline stages for A (0-2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0-2)
BREG => 1, -- Pipeline stages for B (0-2)
CARRYINREG => 0, -- Pipeline stages for CARRYIN (0-1)
CARRYINSELREG => 0, -- Pipeline stages for CARRYINSEL (0-1)
CREG => 1, -- Pipeline stages for C (0-1)
DREG => 1, -- Pipeline stages for D (0-1)
INMODEREG => 0, -- Pipeline stages for INMODE (0-1)
MREG => 1, -- Multiplier pipeline stages (0-1)
PREG => 1, -- Number of pipeline stages for P (0-1)
OPMODEREG => 0 -- Pipeline stages for OPMODE (0-1)


Maybe there is an option in optimization settings that resolve this problem, but I don't know where could be because I try a lot of configurations and any works.

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Registered: ‎07-09-2009

differences between simulation of source and post P&R, 


Simulation of source, for example, handles VHDL sensitivity lists different to the synthesis tools,

     and your post P&R is post synthesis.


And thats one of the easy 'got yas'.


We don't  know your language or tools , but my bet is its a codding problem in the source code,

    have you looked at the warning messages, I know there will be lots, 

        but look for things like latches inferred instead of registers, 


if not obvious,

   break code down into parts, 

       simulate those individualey, both source and post P&R, and see where the difference is .



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Registered: ‎06-21-2017

I thought the OP said that the post synthesis simulation matched the behavioral sim.  This should remove the sensitivity list gotcha.  (I've been there).  If the place & route sim shows different results, doesn't this point to timing?  Does the testbench provide an accurate clock?  Does the design meet timing?  Are there timing constraints?

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Registered: ‎07-09-2009

there is a fundamental difference between simulation of pre and post P&R.


Pre , is simulating your code, 


post is simulating the synthesised code,


It catches us all out at some point, 

   but there can be errors and warnings in your code, that the synthesiser and the simulator interpolate differently.

      As they are errors or warnings, there is no LRM as to what to do, each supplier of the tools has different answers as to what to do when its not specified.


That I'm afraid is how life is,


You are lucky, we normaly get, the simulation works but the real chip puts out different numbers,

    at which point I'd say, do a post P&R simulation, see if that works.



Sorry, you need to go back and look at all those warning and / or error messages you got, and make certain you understand them as being not a problem or fix them.


I'd suggest splitting the code into block, and simulating each block indipendantly,

    see if the post P&R and the pre P&R agree,


at least you will be localising your problem area, 






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