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mrcuchiflis
Visitor
Visitor
1,212 Views
Registered: ‎06-05-2018

Discrete Fourier Transform V4.0

Hello there,

 

I'm implementing the ip core of the discrete Fourier transform V4.0 and I do not understand why I get indeterminate values at the output of the module.

 

My implementation is the simplest possible, 18bits/12point DFT.  This is the test vector I send to XN_RE and XN_IM. 

 

vec_2comp <= ("000010000000000000", "001000000000000000", "001000000000000000",
                          "000010000000000000", "000110000000000000", "000111000000000000",
                          "001100000000000000", "000010000000000000", "001000000000000000",
                          "000011000000000000", "001000000000000000", "000011000000000000");

 

I leave here the simulation.... Can anybody explainme why the XX outcomes?  compare Capture/Capture2

 

Thanks!!

Capture.PNG
Capture2.PNG
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5 Replies
vkanchan
Xilinx Employee
Xilinx Employee
1,158 Views
Registered: ‎09-18-2018

Hi ,

I just checked the code you have provided. You have declared the following signals in your architecture.

 

signal XK_RE: std_logic_vector (17 downto 0) := (others => '0');
signal XK_IM: std_logic_vector (17 downto 0) := (others => '0');

 

These signals are then port mapped to the DFT component

 

Modulo_DFT : dft_0
PORT MAP (
CLK => clk,
SCLR => SCLR,
XN_RE => XN_RE,
XN_IM => XN_IM,
FD_IN => FD_IN,
FWD_INV => '1',
SIZE => "000000",
RFFD => RFFD,
XK_RE => XK_RE,
XK_IM => XK_IM,
BLK_EXP => BLK_EXP,
FD_OUT => FD_OUT,
DATA_VALID => DATA_VALID
);

 

As you see, the ports XK_RE and XK_IM of the DFT are output ports which drive the signals XK_RE and XK_IM you have declared in your architecture.

 

Then in the next line you are driving these signals again with themselves.

 

process (clk)
begin
if rising_edge(clk) then
if DATA_VALID = '1' then
XK_IM <= XK_IM;
XK_RE <= XK_RE;
else
XK_IM <= (others => '0');
XK_RE <= (others => '0');
end if;
end if;
end process;

 

This is wrong as it causes multiple drivers to the output signal resulting in an Unknown value "XXX..X" in the simulation. 

 

The correct way is to simply delete the above process in which you are assigning XK_RE and XK_IM to themselves.

 

Remove them  and directly observe these signals in simulation window. You should be able to observe the DFT IP  driving the outputs with transformed values. The output data is valid only when the Data_valid goes high.

 

 

Regards,

Vivek

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mrcuchiflis
Visitor
Visitor
1,129 Views
Registered: ‎06-05-2018

Hello Vivek,

I already did what you propose and it didnt work; I even deleted the initializations of the vectors.

 

This is the testbench with the changes that you said.

 
TB.jpg
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vkanchan
Xilinx Employee
Xilinx Employee
1,121 Views
Registered: ‎09-18-2018

Hi ,

Can you please share me the .vhd file which you have edited to let me have a look at it .

 

Thanks,

Vivek

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mrcuchiflis
Visitor
Visitor
1,111 Views
Registered: ‎06-05-2018

Hello!

 

here I leave the main .vhd and testbench files. I also leave the DFT IP configuration.

 

A lot of thanks for your help.

DFT.PNG
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vkanchan
Xilinx Employee
Xilinx Employee
1,062 Views
Registered: ‎09-18-2018

Hi ,

The problem is in your source code. If you observe the waveform, when RFFD and FD_IN are high, the input lines XN_RE and XN_IM hold "Undefined values - U". This is what is sampled on the input lines on the next clock cycles. Since the core is seeing invalid data on the first input cycle, it is outputting unknown values "X" at output.

Please see the attached corrected source code and its waveform. In the waveform, the left circle shows valid input data at the first cycle of RFFD and FD_IN going high. Right cycle shows the DFT core outputting valid output.

 

Regards,

Vivek

Waveform_DFT.PNG
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