03-07-2013 02:07 AM
Respected sir I had made a diagram for unit delay using Simulink. Then I generated a verilog code using Xilinx.I had enabled the create testbench option in the system generator. I wanted to know which is the main code and which is the test bench code. I am attaching u the screenshots of them. I request u to see them and reply me.
03-07-2013 10:11 PM
ok sir i sending again.after genrating code and looking waveform we are not able to identifiy which is my out put.
just tell me which file contain my main program and which fille contain testbench.
03-08-2013 06:13 AM - edited 03-08-2013 06:14 AM
Looks like untitled_tb.v is the testbench, untitled.v is the code, untitled_cw.v is the clock wrapper. If you include the .sgp file in an ISE project, it should grab everything for you automatically, though.
03-09-2013 12:00 AM
sir i had design 3 tap iir low pass fiter direct form-2 and coefficient directly genrating from fda tool and assign in my xilinx constant block but while realizing filter model it show 3order and 2 section but i dont want be in 2 section i need to be in only one section as per figure (which i had send) and i dont know which coefficient belong to which side(either left side or ridht side) i am sending snapshot just check and reply....thanks for helping me lot