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5,253 Views
Registered: ‎02-27-2013

Doubt in Verilog code for delay. Urgent reply needed

Respected sir I had made a diagram for unit delay using Simulink. Then I generated a verilog code using Xilinx.I had enabled the create testbench option in the system generator. I wanted to know which is the main code and which is the test bench code. I am attaching u the screenshots of them. I request u to see them and reply me.

ss1.pngss1.png

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7 Replies
Xilinx Employee
Xilinx Employee
5,241 Views
Registered: ‎08-02-2011

Re: Doubt in Verilog code for delay. Urgent reply needed

Can you post larger screenshots?
www.xilinx.com
5,229 Views
Registered: ‎02-27-2013

Re: Doubt in Verilog code for delay. Urgent reply needed

ok sir i sending again.after genrating code and looking waveform we are not able to identifiy which is my  out put.

just tell me which file contain my main program and which fille contain testbench.ss1.png

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ss2.png

ss1.png
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Xilinx Employee
Xilinx Employee
5,220 Views
Registered: ‎08-02-2011

Re: Doubt in Verilog code for delay. Urgent reply needed

Looks like untitled_tb.v is the testbench, untitled.v is the code, untitled_cw.v is the clock wrapper. If you include the .sgp file in an ISE project, it should grab everything for you automatically, though.

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5,212 Views
Registered: ‎02-27-2013

Re: Doubt in Verilog code for delay. Urgent reply needed

thanks for giving information i am really happy but sir as u said there is .sgp file i didn't fing in my image

 

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Xilinx Employee
Xilinx Employee
5,209 Views
Registered: ‎08-02-2011

Re: Doubt in Verilog code for delay. Urgent reply needed

It's that 'untitled_cw.sgp'. Its the one above that says 'Xilinx System Generator Project'
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5,203 Views
Registered: ‎02-27-2013

Re: Doubt in Verilog code for delay. Urgent reply needed

sir i had design 3 tap iir low pass fiter  direct form-2 and coefficient directly genrating from fda tool and assign in my xilinx constant block but while realizing filter model it show 3order and 2 section but i dont want be in 2 section i need to be in only one section as per figure (which i had  send) and i dont know which coefficient belong to which side(either left side or ridht side) i am sending snapshot just check and reply....thanks for helping me lot5.png1.png2.png3.png4.png

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5,182 Views
Registered: ‎02-27-2013

Re: Doubt in Verilog code for delay. Urgent reply needed

please solve this problem

 

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