cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
4,392 Views
Registered: ‎01-05-2010

Doubt in connecting clock port of Black Box while connecting it to Microblaze via FSL bus

Hi  There :-)

 

I had imported a verilog file which consisted of synchronous logic to System Generator as a black box.

 

My verilog code is as follows:-

 

                             /*  customlogic.v  */

/---------------------------------------------------------------------------------------------/

module  customlogic(

output  reg  [31:0] sum,

input    wire  [31:0] a,

input    wire  [31:0]b,

input    wire            clk,ce

)

always @ (posedge clk)

begin

  sum <=  a + b;

end

 

endmodule

 

/---------------------------------------------------------------------------------------/

In the EDK processor  token I changed my bus connections from PLB to FSL.

 

When I tried to connect it to the Microblaze through the FSL link but the ports  'clk'  and 'ce'  which  would be synchronized

automatically if I connected it to a PLB bus is now left open.

 

Should I connect it to "sys_clk_s" that exists in the dropdown list in ports window?

 

And which port should I connect my FSL_CLK, FSL_FIFO_R_CLK, FSL_FIFO_W_CLK to?

 

The version of tools I am using are Xilinx ISE 10.1, XPS 10.1,System Generator 10.1

 

The board I am using is Virtex 2 Pro (XC2VP30-7FF896).

 

Thank you and regards,

anand

0 Kudos
4 Replies
ticktack
Explorer
Explorer
4,374 Views
Registered: ‎08-14-2007

Firstly you need to take a look at Black Box HDL Requirements and Restrictions (page 328 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/sysgen_user.pdf)

 

Then take a look Export as Pcore to EDK section(page 389)

0 Kudos
4,359 Views
Registered: ‎01-05-2010

Hi ticktack :-)

 

I guess I have followed all the rules required to connect the black box . The simulation is working fine.

 

The clock is connected to a default SPLB clock when I connect my peripheral to the PLB bus of the Microblaze processor.

However when I connect it to the FSL bus of Microblaze to my custom peripheral the clock port is being shown in the Ports

window of XPS and I do not know which port to connect it to.

 

Should I configure it in System Generator to connect it to the default FSL bus clk  or should it be configured in XPS?

 

Should I use some DCM etc?

 

I keenly await a response.

Thank you :-)

0 Kudos
ticktack
Explorer
Explorer
4,328 Views
Registered: ‎08-14-2007

I think EDK project will use DCM. I'm not familar at the Embedded side. Normally you should be able to see clock ports in MHS. I guess sys_clk is used.

0 Kudos
4,319 Views
Registered: ‎01-05-2010

Thank you :-)

 

I shall check it out :-)

0 Kudos