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Adventurer
Adventurer
11,131 Views
Registered: ‎08-20-2007

EDK Pcore Export with FSL bus connection. Different CLK frequencies.

Hello.
I have a question. I'm using System Generator as a Pcore for Microblaze project in EDK.
I use From Register and To Register blocks to access Pcore from Microblaze and FSL bus to connect Pcore to Microblaze in EDK project.
Everything works fine, but I need a little bit else.
The problem, that my clock source is 48Mhz for Spartan3, but inside I'm using DCM to generate 50Mhz, because it required by some IPcores for Microblaze. But I want my Sysgen Pcore to run at 48Mhz, because this frequency allows beter divide of Sample frequenciesin Sysgen.
So question is: Can Sysgen and Microblaze run on different frequencies? What clock then should be connected to FSL buses?
My previus attempt with 24Mhz clock for Sysgen and 50Mhz for Microblaze was unsuccesfull.
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Visitor
Visitor
11,095 Views
Registered: ‎09-13-2007

Syoma,
 
I am also investigating the possibility of clocking my Sysgen pcore and Microblaze at different rates. Let me know if you have any updates on this question.
 
Are you using "Configure Co-Processor" in XPS to setup your EDK pcore via FSL bus and then manually editing your .MHS file to wire your clock signal to your Sysgen algorithms in XPS?
 
Also, I am using ISE/EDK/Sysgen 9.2.
 
--Somit
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Visitor
Visitor
11,082 Views
Registered: ‎09-13-2007

Syoma,
 
I think we may have a solution to clocking your Sysgen pcore and Micro/FSL at different rates. The FSL bus has an asynchronous option. For example, I want to clock my Sysgen pcore at 100MHz and my Micro/FSL at 125MHz. I'd select an asynchronous (instead of synchronous) FSL bus and set my FSL_S_Clk and FSL_M_Clk appropriately.  
 
You also need to set the C_ASYNC_CLKS=1 and C_READ_CLOCK_PERIOD appropriately. In my case, I'd set C_READ_CLOCK_PERIOD = 8000ps or C_READ_CLOCK_PERIOD = 10000ps
 
I will let you know when I have results.
 
-Somit
 
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Adventurer
Adventurer
11,071 Views
Registered: ‎08-20-2007



Are you using "Configure Co-Processor" in XPS to setup your EDK pcore via FSL bus and then manually editing your .MHS file to wire your clock signal to your Sysgen algorithms in XPS?

No I'm using the technique, described in Sysgen help. I'm exporting Sysgen model as Pcore and use To and From Registers in Sysgen. Then in EDK I isert instance of my peripheral and connect it by FSL bus to Microblaze. Then in Tab "Ports" I define port connections of my Instance. And here are comming the questions - to which nets connect the CLK inputs of FSL buses?
Before I worked with version 8.1 of Xilinx tools, and found, that in 9.2 FSL drivers for Sysgen became much better.  There is a polling mode avaliable - in this mode MB waits untill it gets responce from FSL bus. This mode should be usefull if Sysgen works with other frequency. This possibility even was mentioned in API guide for PCORE.
So right now I know, that MB and Sysgen cores can be clocked with different frequencies. The only question to which clock connect FSL bus - to Mb or to Sysgen?
But there are only two posiibilities and I see no problem to check them both.
Unfortunately the problem is not so urgent for me, so I don't have time to test it.
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Xilinx Employee
Xilinx Employee
11,066 Views
Registered: ‎08-07-2007

If you require asynchronous peripherals then you should specify your FSL peripheral as asynchronous, then you will have a master and a slave clock input.  You would set the master to the MicroBlaze clock and the slave to the System Generator peripheral clock.

It sounds like your design does not require asynchronous clocks however, unless you are interfacing with something external at the 48MHz rate it can be synchronous.  The System Generator portion of your design should be set up with relative sample rates throughout which will create the same ratios regardless of the actual clock speed.  The only reason you would need asynchronous is if 48MHz is required at the interface between the System Generator peripheral and whatever it interfaces to.

For further details about how to configure an FSL peripheral or about System Generator sample rates please open a webcase with Xilinx support:
http://support.xilinx.com/support/clearexpress/websupport.htm
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Adventurer
Adventurer
11,057 Views
Registered: ‎08-20-2007

So, if I understood right, to use different clock frequencies, I should configure Fsl_v20 IP core with option "FIFO in FSL operates Asynchronously" and connect appropriate clock sources to FSL_S_CLK and FSL_M_CLK.
Looks simple.
Thanks.
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