We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer stevet
Registered: ‎10-10-2018

ENOB increase using the FIR Compiler



I am using FIR Compiler 7.2 to create a FIR filter and decimation.  The input to Filter and Decimation is 24 bits wide, the decimate reduces the sample rate by a factor of 6.  Since you achieve a 1 bit increase for a factor of 4 over-sampling my new bit length should be 26 bits, am i correct in assuming this?

Should i then set my output width to 26bits and select one of the output rounding modes using the configuration GUI?





Tags (4)
0 Kudos
1 Reply
Registered: ‎08-16-2018

Re: ENOB increase using the FIR Compiler

FIR performs the multiply and add operation, therefore your output width depends on the 'filter coefficient' width and "input singal" width.

You can check the full scale width for the above values in the FIR IP as well. It will give you both the total width and the fractional width. Based on fractional width, we can decide the total number of bits. For example if total output width is 12 and fraction width is 7. Then we can set total width from 5 (i.e. no decimal after rounding) to 12 (i.e. full scale output)

/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
0 Kudos