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Observer
Observer
12,153 Views
Registered: ‎09-10-2007

ERROR,, I want to h/w co simulation of system generator help me!

 i make "jtag co sim" blockset. but always this error appear,, i don't understand this error,,,what means?
 
ERROR:NgdBuild:76 - File
   "D:/FPGA/pld_user_exampls_CAFE/dsp_lab3/labs/lab3/netlist_hw/xflow/jtagcosim_
   iface_virtex.ngc" cannot be merged into block "jtag_iface"
   (TYPE="jtagcosim_iface_virtex") because one or more pins on the block,
   including pin "re", were not found in the file.  Please make sure that all
   pins on the instantiated component match pins in the lower-level design block
   (irrespective of case).  If there are bussed pins on this block, make sure
   that the upper-level and lower-level netlists use the same bus-naming
   convention.
 
ERROR:NgdBuild:604 - logical block 'jtag_iface' with type
   'jtagcosim_iface_virtex' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, or the misspelling of a type name.
   Symbol 'jtagcosim_iface_virtex' is not supported in target 'spartan3e'.
WARNING:NgdBuild:443 - SFF primitive
   'hwcosimtoplevel/sysgen_dut/default_clock_driver/xlclockdriver_1/clr_reg/has_
   latency.fd_array[1].reg_comp_1/fd_prim_array[0].rst_comp.fdre_comp' has
   unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'hwcosimtoplevel/sysgen_dut/bandpass_filter_x0/dafir_v9_0/core_instance/valid
   _pipe/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp'
   has unconnected output pin
 
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

*** ERROR ***
An error was encountered while running xflow.  Please refer to the log xflow.results for further information.
 
 


Message Edited by zalove on 09-13-2007 01:12 AM
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Explorer
Explorer
12,148 Views
Registered: ‎08-14-2007

What's version of System Generator? You can't genenrate a JTAG Hardware In the Loop (HITL) Hw-CoSim Target for a Spartan-3e if the System Generator version is older than 8.2.02i.
 
Update to System Generator 9.1 or 9.2 should solve the problem.
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Xilinx Employee
Xilinx Employee
12,136 Views
Registered: ‎08-07-2007

This issue is documented in answer record 24381 as well:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=24381

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Observer
Observer
12,133 Views
Registered: ‎09-10-2007

thank you! i uderstand this error,,,,,,, my sysgen 8.2,,ise8.2,,matlab r14 sp3,,,
 
i don't have sysgen 9.1 or 9.2,,, but, thank you everone!! ^o^
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Observer
Observer
11,967 Views
Registered: ‎09-10-2007

Hello zalove,
 
Did you figure out the warning:'
WARNING:NgdBuild:443 - SFF primitive
   'hwcosimtoplevel/sysgen_dut/default_clock_driver/xlclockdriver_1/clr_reg/has_
   latency.fd_array[1].reg_comp_1/fd_prim_array[0].rst_comp.fdre_comp' has
   unconnected output pin'?
 
I have the same warning. Does it really matter? Is this something related to the code? But the code is generated by systemgenerator...
 
Or, does anyone else know anything about this?
 
Thanks in advance!
 
====================================
er....I thought your error was generating when using ISE....seems like it's not...?


Message Edited by beibei.jiao on 10-12-2007 03:20 PM
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Xilinx Employee
Xilinx Employee
11,927 Views
Registered: ‎08-07-2007

The warning you have listed here is different than message originally reported in this thread.  Please create new threads for different issues/questions

This warning message is benign and can be ignored. 

If you would like further details please open a WebCase with Xilinx Tech Support 
http://www.xilinx.com/support/clearexpress/websupport.htm
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