Edge-transition detector

[dagdago]

Hello again,

I wish to detect rising- and falling-edge of a counter output using system generator.

I've written the following state machine and used an MCode block to host it.

function [fall,rise] = edge_detect(din)

persistent state, state = xl_state(1,{xlUnsigned, 3, 0});
% state 0 indicates '0' state
% state 1 indicates '1' state
% state 2 indicates 'rising-edge' state
% state 3 indicates 'falling-edge' state

switch state
    case 0
        if din == 0
            state = 0;  % '0' state
        else
            state = 2;  % rising-edge
        end
        fall = false;
        rise = false;
    case 1
        if din == 0
            state = 3;  % falling-edge
        else
            state = 1;  % '1'
        end
        fall = false;
        rise = false;
    case 2
        if din == 0
            state = 3;  % falling-edge
        else
            state = 1;  % '1'
        end
        fall = false;
        rise = true;
    case 3
        if din == 0
            state = 0;  % '0'
        else
            state = 2;  % rising-edge
        end
        fall = true;
        rise = false;
    otherwise
        state = 0;
        fall = false;
        rise = false;
end

The problem is I keep getting error messages as follows:

Error("edge_detect.m"): line 11:16 the '==' operator cannot have one Bool type and one UFix type operands
Error("edge_detect.m"): line 19:16 the '==' operator cannot have one Bool type and one UFix type operands
Error("edge_detect.m"): line 27:16 the '==' operator cannot have one Bool type and one UFix type operands

The block accepts a boolean type signal fed from an up counter and a Convert block casting it to boolean.

I've triied using comparing 'din' to flase and true but this rout generated the following error:

Error("edge_detect.m"): line 11:19 flase is not assigned with a value before this point. A misspelling or a switch statement without otherwise statement may cause this error.
Error occurred during "Block Configuration".

Couldn't anyone direct me in the right direction?

Thanks, dag

[eilert]

Hi,

be careful with the types you use.

It is not (really) your fault.

When sysgen says "boolean" it means std_logic, which uses values of '1' and '0' here.

Also a scalar might be different compared to a vector with 1 element.

(boolean /= UFix_1_0; or: std_logic /= std_logic_vector(0 to 0) ).

But you better check this with the tools.

So, depending on what you are using as the type for Din you might see some funny behavior

since the code does not show what types appear at the expression

din == 0

It seems like you already have eliminated the typo that caused the  last error message (flase is not assigned...).

Besides:

Your FSM is a very correct formal approach.

It just requires a lot of code.

A 2-stage shiftreg and two and2b1 Gates (with registered outputs if needed) would do the same.

Wether there is a difference in HW- ressources depends on the actual implementation of the FSM.

Have a nice synthesis

   Eilert

[dagdago]

Thank you Eilert.

I've eventually ended up with a solution similar to what you suggested.

I've used an up sampler to increase the input sampling frequency. I then performed an AND logic operation over the upsampled signal and its not unit delay.

BTW, when should someone use an output register?

Dag

[eilert]

Hi Dag,

you asked "when should someone use an output register?".

If possible, always.

Unless you have good resasons for not synchronizing the outputs. But these are rare.

Synchronized (registered) outputs prevent the creation of long combinatorical chains and feedback loops.

Furthermore the synthesis can create a very fast circuit since the combinatorical paths between the registers can be kept short.

(Optimum: one LUT per FF)

Have a noice synthesis

  Eilert