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7,967 Views
Registered: ‎06-10-2016

Error: An error occurred when creating the Vivado project... Block: Unspecified

I am taking the sysgen tutorials and following ug948-vivado-sysgen-tutorial.pdf . I am not able to generate to compile the design into hardware.    

 error.JPG

 

Summary of Errors:
Error 0001: ERROR: An error occurred when creating the Vivado project...
Block: Unspecified
--------------------------------------------------------------------------------

Error 0001:

Reported by:
Unspecified

Details:
ERROR: An error occurred when creating the Vivado project.
error copying "{C:/Users/Namrata
Kogalur/Desktop/mitacs/project/ug948-design-files/SysGen_Tutorial/Lab1/netlist/sysgen/lab1_1_clock.xdc}":
no such file or directory
INFO: [Common 17-206] Exiting Vivado at Fri Jun 10 11:28:07 2016..

 

I have attached my model.

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4 Replies
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Xilinx Employee
Xilinx Employee
5,623 Views
Registered: ‎08-01-2008

are you getting this error with all the designs are specific to current design . This can be installation issue is all designs failing with same error

Thanks and Regards
Balkrishan
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Contributor
Contributor
3,245 Views
Registered: ‎04-28-2017

Hello Namrata,

 

I had the same problem. The issue is this: In your file path, there is a space in "Namrata Kogalur". Xilinx does not like path/file names with spaces. Move the project to a different directory without spaces in the name. Your design will then be able to find the correct XDC file. Good luck!

 

Aditya

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Visitor
Visitor
1,352 Views
Registered: ‎05-10-2018

Error has been resolved by deselecting the option "Post-synthesis" in the system generator token in the compilation tab.

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Newbie
Newbie
572 Views
Registered: ‎09-19-2019

Hi
i couldnt find post-synthesis in my system generator token in the compilation tab.
can you show it by sending an image?
thanks
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