Error [Coretcl 2-1132] when using System generator to generate the IP core

[corazon_0513]

There is a error was reported when I using System Generator tool to generate the IP catalog:

ERROR: [Coretcl 2-1132] No IP matching VLNV 'User_Company:SysGen:lab2_3_sol:1.0' is accessible for the current part 'xazu3eg-sfvc784-1-i'.

It seems like that this error is only reported when I choosing the Part is Automotive Zynq UltraScale+ seriers, others series are unaffected.

How should I deal it?  Thanks!

[sabankocal]

Hi @corazon_0513 ,

Is this solution also solves yours?

Regards

[corazon_0513]

Thanks for your reply! @sabankocal

Maybe I didn't describe this problem clearly , my english skill is not good.

Referencing UG948，I'm studing that how to using system generator to generate IP catalog. this simulink project is a copy of Xilinx official demos.

When I using default part "xc7k325t", it can generate the ip catalog successfully.

I have a development board which using "xazu3eg" chip, This problem showed when I trying change the part from default "xc7k325t" to "xazu3eg".

Without any other change, just modify the part to "Automotive Zynq UltraScale+" series, the generate process will failed and reported error messages.

That's weird, I tryed choosing "Zynq UltraScale+:xczu3eg" and "Automotive Zynq: xa7z010", both can be generated successfully.

If there is anything unclear in my description, please reply me!

Thanks for your reply again!

[sabankocal]

Hi @corazon_0513 ,

It can be license related problem. which license are you using?

For example, node locked licenses can be used only related devices.

Regards

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if(solves_problem) mark_as_solution <= 1'b1 else if(helpful) Kudo <= Kudo + 1'b1

[corazon_0513]

Thanks a lot for your reply  @sabankocal 

I'm a student and my development environment and license is configuted by my senior. 

If this is an licenses problem, I think that the “30 Day Trial” can slove it.

It say that "You will be able to target every Xilinx device and run all Xilinx applications".

That's mean it should allow all devices can be choosed as System Generator project's target right?

I tryed enable “30 Day Trial” and regenerate, but the problem still exist.

Is this attested that it might not be a license problem? 

Thank you again:)

[sabankocal]

Hi @corazon_0513 ,

It means, your problem is not license related.

If I were you, I'd concantrate to differences between two devices, that are needed for your IP core.

Just for example: Your IP core needs some high speed pins(GT), one of them has it, but other has not.

Regards,

Saban

[corazon_0513]

Thank you @sabankocal !

I just tryed make a new simplely System Generator model, which only have "Input, Logic not, Output"

"Gateway In" sample period is 1/20E+04 which means sample freq is 200KHz, I think it's enough slow speed to pins.

Notwithstanding that, the error is still existing. 

One more strange point is that, the new simple test project and old offical demo project have different "Reported by" model. Like this.↓

That's makes me unable to determine which module in project cause this problem.

In fact, I've tested many demos of UG948. All of those demos can't generate IP core on "Automotive Zynq UltraScale+".

I guess, maybe the problem isn't related to what module I've used in projects? But I have no idea of which factor can cause this problem.

By the way, I've been reinstall Vitis_2019.2, but it's doesn't deal this problem.

Are there any other possible causes of this problem?

Thank you very much and look forward to your reply, Saban:)

Regards,

Jerry

[corazon_0513 · Accepted solution]

I have a new discovery.

When I trying run "ProjectGeneration.tcl" file which generated by System Genrator, I see the same error reported at Vivado Tcl console.

And I saw that:

It says that 'azynquplus' is unrecognized family, so I checked that “Automotive Zynq UltraScale+” series is 'zynquplus' family.

THERE AREN'T HAVE 'a' BEFORE THE 'FAMILY' NAME.

After got this conclusion, I changed 'DSPfamily' in file 'ProjectGeneration.tcl'.

Then, I opened Vivado and run this tcl script, the IP core generated successfully!

Every time the System Generator regenerate the IP core, I need change this file manually.

I'm a newbie, and I'm not sure is this true way to deal this problem.

Thanks for @sabankocal's help!!!

And wish this problem have a prefect solution!

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Update: I found a better way deal this problem: 

When we choosing "Part", it can be choosed as "Zynq UltraScale+" to replace "Automotive Zynq UltraScale+",  like this: "xazu3eg-sfvc784-1-i" to "xczu3eg-sfvc784-1-i".

That's allow we successfully complete generate process.

After that, modify ProjectGeneration.tcl file, change "xczu3eg" to "xazu3eg", and using Vivado run this .tcl file. That's All.