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Newbie km41
Registered: ‎09-19-2012

Error during bitstream generation



I'm using a Virtex II pro for doing some audio implementations in it. I used THIS guide to make my virtex have sound as input and output.


Here is a small description of the package I used:

Audio Design with a Hardware Board Support Package
This QuickStart demonstrates the ability to generate standalone audio designs from System Generator for DSP targeting the XUPV2P development system. The key to this is an HDL wrapper that contains the interface logic to the audio CODEC.


And here is the problem that I have...


When I generate a very simple design using the system generator token, an error appears, which I don't know how to confront...


Checking timing specifications ...
ERROR:XdmHelpers:682 - Second definition of specification "TS_clk_43f2427a"
   first definition: PERIOD:clk_43f2427a:10000:pS:HIGH:50%
   second definition: PERIOD "clk_43f2427a" 10000.000000 pS HIGH 50.000000 %
Checking expanded design ...


Is it a bug or something? I use Matlab R2006b, Xilinx ISE 9.1 sp3, and System Generator for DSP 9.1. I used to have ISE 10.1 and sysgen 10.1 in the past (with the wrapper for the audio codec running properly), but some sysgen blocks (like FIR) were not compatible with my virtex II pro. That's why I changed to 9.1, but other new problems appeared.


So I have three questions to make:

a. What's wrong with the double definition of this clock period? Can I fix this somehow? (I attach my full xflow.log file)


b. Can I install ISE and sysgen 10.1 again and make the FIR block compatible with Virtex II pro?


c. If I change from Virtex II pro to Virtex 4, will the wrapper in the guide above be installed in the same manner? Will it work properly, or it's just for v2pro boards?


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1 Reply
Newbie km41
Registered: ‎09-19-2012

Re: Error during bitstream generation

Wrong link above, the package is here. http://www.xilinx.com/univ/xupv2p.html

Audio Design with a Hardware Board Support Package

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