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ankitkes2
Observer
Observer
224 Views
Registered: ‎07-10-2018

Error during hardware software co-simulation using ZCU102 board

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hi,

I am trying to do hardware software co-simulation using ZCU 102 zynq ultrascale board. I am able to generate hardware software co-sim block as shown below:

ankitkes2_0-1614078116343.png

but when I add add this block to simulink and try to run i get the following error:

ankitkes2_1-1614078685589.png

 

it tells that "could not find device". but i connected the FPGA board with PC through JTAG. 

How can I solve this issue>

Thanks

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ravidapu
Xilinx Employee
Xilinx Employee
44 Views
Registered: ‎12-14-2017

Hi,

This board has an issue with JTAG connection in Sysgen, this is known issue. In the latest Vivado releases we stopped supporting HW cosim for this board as the team wants to revamp the flow for all the boards in the coming releases, it will take some time. I hope this helps

ravidapu_0-1614745545483.png

 

 

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ravidapu
Xilinx Employee
Xilinx Employee
184 Views
Registered: ‎12-14-2017

Hi,

It seems like the Hardware is not connected to PC through JTAG properly. Before simulating the HW cosim library block, make sure the hardware is properly connected to the machine through JTAG. You can do so using Vivado Hardware manager wizard. If the connection is established this error will go away

Hope this helps

Regards,

Raju A.

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ankitkes2
Observer
Observer
162 Views
Registered: ‎07-10-2018

Hi @ravidapu ,

Thanks for your response.

I connected the hardware properly. I also go to hardware manager manually to connect as shown below:

ankitkes2_0-1614151452170.png

But when I am running the simulation, same error is coming.

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ankitkes2
Observer
Observer
159 Views
Registered: ‎07-10-2018

Hi, @ravidapu 

I just find out that part number of zcu102 board shown in system generator token and hwcosim block has a difference of one alphabet , shown in below images:

ankitkes2_1-1614152275281.png

ankitkes2_2-1614152303295.png

Is this a reason for error?

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ravidapu
Xilinx Employee
Xilinx Employee
107 Views
Registered: ‎12-14-2017

Hi,

Yes, that is the actual issue but I am wondering why the parts are different, are you using the zcu102 evaluation board only ? Please make sure you are using correct board

I can also confirm that the part in sysgen for zcu102 evaluation board is correct, you can check the same in Vivado as well

Hope this helps

Regards,

Raju A.

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ankitkes2
Observer
Observer
96 Views
Registered: ‎07-10-2018

Hi @ravidapu

yes I am using ZCU102 board, image of board is shown below:

ankitkes2_3-1614316281038.png

in the vivado project generated from system generator during hardware software cosimulation , it is showing the part no shown in below image.

ankitkes2_4-1614316447627.png

and also I have generated many vivado projects from system generator for the same board and they run on zcu 102 board. issue is only coming when using hardware software cosimulation. 

What could be possible reason?

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ravidapu
Xilinx Employee
Xilinx Employee
45 Views
Registered: ‎12-14-2017

Hi,

This board has an issue with JTAG connection in Sysgen, this is known issue. In the latest Vivado releases we stopped supporting HW cosim for this board as the team wants to revamp the flow for all the boards in the coming releases, it will take some time. I hope this helps

ravidapu_0-1614745545483.png

 

 

View solution in original post

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