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Visitor
Visitor
3,107 Views
Registered: ‎02-22-2010

Error in Synthesize RTL stage

I'm using AccelDSP for my project.I've created the floating point matlab codes and verified and generated the fixed point representation. I've set all the quantization directives after which I get no errors.

The Verified fixed point, generate RTL, Verify RTL steps pass successfully.  But I get the following error message when running the Synthesize RTL step.

 

#ERROR:Xflow - Program xst returned error code -1. Aborting flow execution...
#(      E-SYNTH-0001): Synthesize Verilog with XST failed via return code.
#        Explanation: Return value: child process exited abnormally
#

#(      E-SYNTH-0001): Synthesize Verilog with XST failed via return code.
#        Explanation: Return value: child process exited abnormally
#
#

#Synthesizing RTL design for language 'Verilog' using tool 'XST' FAILED
#(    I-GENERAL-0001): Time elapsed: "638.28" seconds
#0

 

 I don't think that this is something due to the error in our design code. Is it an issue in the AccelDSP ? It would be grateful if somebody could explain me a way to correct this issue ? 

 

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Xilinx Employee
Xilinx Employee
2,884 Views
Registered: ‎08-07-2007

I would suggest going into the HDL folder for your AccelDSP project and looking for a report file (.syr I believe for XST) also, adding those HDL files directly to a new ISE project and try synthesizing the generated HDL files there.  You should get a better explaination for the error.  If AccelDSP is writing out incorrect HDL code you may try changing the language used (VHDL or Verilog) and ultimately you may need to find the root cause in the M-script and have to modify how part of your code is written to workaround this.

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