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onasvi_singh
Newbie
Newbie
509 Views
Registered: ‎02-25-2019

Error in simulation of Xilinx Sytem blocks

Hi,

We are working on our project (Interplation and decimation for Multirate singal processing using FPGA).For the above purpose we have been using the following products:-

Matlab 2011a

Xilinx 14.1

Also we are using the Vivado Design Suite:- 30 day evaluation license

We have been using Xilink blockset in Matlab simulink to design a circuit with the following blocks:-

Input Discrete Sine wave

GatewayIN

Gain

Delay

Downsample/Upsample

GatewayOut

System generator

Scope

A circuit was designed and executed using these blocks. No error was recieved as such but the scope failed to show any signs of output too. Tried changing all the parameters of the blocks too,result still the same. Can this be because of a licensing error?or does certain blocks have different licensing period.

Kindly help us with the query,

Thank You.

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3 Replies
meherp
Moderator
Moderator
458 Views
Registered: ‎08-16-2018

The issue is not related to license. 

Note that, you need to connect the scope with the output of the "GATEWAY OUT" port. 
If this does not work, then can you please share the design (or screenshot of the design). 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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onasvi_singh
Newbie
Newbie
425 Views
Registered: ‎02-25-2019

Thank you for the previous reply,

My problem is still not resolved though. GATEWAYOUT was already connected to the scope,yet no output was shown. Below attached is the circuit which we are working on. Kindly help us with the same. The output in the scope is still not visible.Capture.JPG

Capture.JPG
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vkanchan
Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎09-18-2018

Hi @onasvi_singh ,

Can you please debug the design by probing the output on sope at each block in the design, this way it can provide you an idea if there is an issue with output of a block in the design.

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