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onasvi_singh
Newbie
Newbie
413 Views
Registered: ‎02-25-2019

Error in simulation of Xilinx blocks

Hi,

We are working on our project (Interplation and decimation for Multirate singal processing using FPGA).For the above purpose we have been using the following products:-

Matlab 2011a

Xilinx 14.1

Also we are using the Vivado Design Suite:- 30 day evaluation license

We have been using Xilink blockset in Matlab simulink to design a circuit with the following blocks:-

Input Discrete Sine wave

GatewayIN

Gain

Delay

Downsample/Upsample

GatewayOut

System generator

Scope

A circuit was designed and executed using these blocks. No error was recieved as such but the scope failed to show any signs of output too. Tried changing all the parameters of the blocks too,result still the same. Can this be because of a licensing error?or does certain blocks have different licensing period.

Kindly help us with the query,

Thank You.

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meherp
Moderator
Moderator
359 Views
Registered: ‎08-16-2018

Hi, 

Can you please share the design or give a screen shot of it. 

 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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