Error on insufficient LUT in zedboard after hardware cosimulation in system generator
I have designed several control loops with system generator mostly to drive a three_phase motor and most of them I burnt on zedboard with no trouble in generation.
There is yet another model which I have designed which is very similar to the rest, but I am constantly receiving this error that says the design requires 65300 LUTs while the board has only 53200!!!
I have simplified the model, used extra pipelining, different methods for sythesizing and.... to overcome, but, still this annoying error persists. The design is not really intricate. I don't know what is eating up the LUTs?!
To my very much frustration of working on this for more than two weeks now, this has even taken me to the point to question that if such a simple control without any intricate DSP cores cannot be done on zedboard because of insufficient LUTs, then the whole concept of using FPGA for such purposes is absurd since they cannot compete with any microcontroller.
Any help in this regard to solve the LUT problem is very much appreciated.
Do you know what part of your design is using too many LUTs? Open your synthesized design and click on Report Utilization. You should get a report showing utilization by hierarchy. This will tell you what areas to work on.
Do you have a large IP in a generate loop? Something like a CORDIC or a divide can eat up LUTs, and if you have a bunch of them, you can use up all the LUTs. Are you using floating point where fixed point will do? Can you map any functions to DSPs or into a BRAM lookup table?