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Newbie iosman123
Newbie
326 Views
Registered: ‎06-29-2019

Error simulating Virtex-5 DSP48E slices

Hello,

 

I have a project where I am implementing the equation P = C - (A * B) using a DSP48E slice (Virtex-5 SX95T device). To implement such equation, I am instantiating a DSP48E slice and configuring te Opmode input to b"011_0101" and the ALUMODE input to "0011".  While running the simulation in modelsim I realized the result on the P output was incorrect.  Rather than subtracting (as specified by ALUMODE = 3), C is being added to the A*B product.Then, just for kicks, I changed the ALU mode to "0000" (which is supposed to implement P = C + (A*B)) and to my surprise the result was C - (A*B).  Obviously, the behavior of the ALUMODE register is swapped in the Unisim model for the DSP48E.  To make matters even more interesting, I tried implementing P = PCIN - (A*C), and for this equation the ALUMODE does work as expected (ALUMODE = 3 results in subtraction, the correct behavior).

 

I have the following questions for you kind people:

 

1. Has anyone out there run into the same issue while implementing P = C - (A*B)?

 

2. Do you see anything I could be missing in terms of configuring the DSP48E slice to attain the correct behavior?

 

3. If you have used the DSP48E slice successfully to implement the equation in question, did you use Verilog or VHDL models?

 

My design is written in VHDL, I am using ISE 9.2.0.4 and Modelsim PE 6.2E

 

thanks

iosman

 

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3 Replies
Xilinx Employee
Xilinx Employee
216 Views
Registered: ‎07-11-2019

Re: Error simulating Virtex-5 DSP48E slices

Hello @iosman123 

I was wondering if you would be able provide the dsp code and testbench code you are using to simulate your DSP?

To answer your third question, it should not matter whether you are using Verilog or VHDL, use the one you are most comfortable using!  

Lastly, I am not sure if you used this to create the code for your dsp, but vivado has template code for the DSP48E1/2 slices under tools > language template > device macro instantiation > (your specific device) > DSP48. 

I hope this helps! Please provide your code so I can take a look at what is happening. 

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Scholar drjohnsmith
Scholar
206 Views
Registered: ‎07-09-2009

Re: Error simulating Virtex-5 DSP48E slices

Dont instantiate a DSP48, infer,

BTW: that ISE is WELL old, cant you move up to 14.7 ?
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Xilinx Employee
Xilinx Employee
180 Views
Registered: ‎07-11-2019

Re: Error simulating Virtex-5 DSP48E slices

@drjohnsmith , @iosman123 

I agree. Inferring the DSP requires much less time and programming. However, to get the most control over the DSP slice, if that is what you need, instantiation is necessary. Also, moving to ISE 14.7 will allow you to get more features and the most updated ISE version, so I would also recommend doing that. 

Instantiating vs Inferring: https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_imp_instantiation_and_inference.htm

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