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tdurand
Participant
Participant
516 Views
Registered: ‎10-19-2020

Error when following the tutorial Versal ACAP AI Engine A to Z Bare-metal Flow

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I'm trying to get through the above tutorial, located here:  https://github.com/Xilinx/Vitis-Tutorials/tree/master/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z

I'm running 2020.2.

I got to the third page, Step 1. Modify the Graph for Use in Hardware Build.  When I rebuild the target for hardware, I get these errors.  Can someone help interpret them?

ERROR: [CFGEN 83-2284] No stream resources found that can accomodate compute unit "ai_engine_0.DataIn1"
ERROR: [SYSTEM_LINK 82-36] [13:23:39] cfgen failed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1663.457 ; gain = 0.000 ; free physical = 31119 ; free virtual = 220942
ERROR: [SYSTEM_LINK 82-62] Error generating design file for ..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: ..../Xilinx/Vitis/2020.2/bin/cfgen -dmclkid 0 -r ..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/sys_link/_sysl/.cdb/xd_ip_db.xml -i ..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/sys_link/cfgraph/aie_cfgraph.xml -o ..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [13:23:39] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1682.477 ; gain = 0.000 ; free physical = 31157 ; free virtual = 220980
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [binary_container_1.xclbin] Error 1

13:23:39 Build Finished (took 45s.591ms)

For what it's worth, before following the tutorial from the above location, I found another version of it here:  https://xilinx.github.io/Vitis-Tutorials/master/docs/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/03-pl_application_creation.html

I was able to get a little bit further with that version, but it failed at Step 4. Build the System.  I got these errors:

ERROR: [VPL 31-306] MIG Core Generation Failed.
ERROR: [VPL 60-773] In '..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/vivado/vpl/vivado.log', caught Tcl error: problem implementing dynamic region, impl_1: opt_design ERROR, please look at the run log file '..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: opt_design ERROR, please look at the run log file '..../simple_application_system_hw_link/Hardware/binary_container_1.build/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [13:58:44] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:08 ; elapsed = 00:09:24 . Memory (MB): peak = 1682.477 ; gain = 0.000 ; free physical = 25220 ; free virtual = 215078
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [binary_container_1.xclbin] Error 1

Which of these tutorials is the latest and greatest?  There were some differences between the two.

Lastly, one more question -- each of the tutorials instructs to start with the "Versal VCK190 Evaluation Platform".  Will they also work with the "Versal VCK190 ES1 Evaluation Platform" (which I think is what I'm using)?  I followed the directions, wondering if it would work on my hardware, but I haven't been able to get that far using either tutorial.

Thanks,

Tom

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torid
Xilinx Employee
Xilinx Employee
491 Views
Registered: ‎08-01-2007

Hi Tom, 

Basically it's saying that it's trying to build the hardware link project and connect up the system and can't connect the AIE input at the top level. If this is Step 1 of the 3rd section (as shown below), you only want to be building the AIE application. We haven't added the PL kernels or configured the hw_link project so it's not ready to build the whole system yet. 

 

torid_0-1620255933411.png

 

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torid
Xilinx Employee
Xilinx Employee
492 Views
Registered: ‎08-01-2007

Hi Tom, 

Basically it's saying that it's trying to build the hardware link project and connect up the system and can't connect the AIE input at the top level. If this is Step 1 of the 3rd section (as shown below), you only want to be building the AIE application. We haven't added the PL kernels or configured the hw_link project so it's not ready to build the whole system yet. 

 

torid_0-1620255933411.png

 

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tdurand
Participant
Participant
485 Views
Registered: ‎10-19-2020

Some updates - I got further on the first version of the tutorial I had listed above, here:  https://github.com/Xilinx/Vitis-Tutorials/tree/master/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z

- I was hoping the error in my initial post would go away when I added the mm2s.cpp and s2mm.cpp, and it looked like it did.  So, the above step failed to compile, but I kept going further and was then was able to compile everything successfully at the end.  (Maybe when Step 3 says "Change the Active build configuration to Hardware and rebuild the project", it meant to rebuild only the AIE project?)

- Am not yet able to run the application (Step 4. Run the System).  I think, not sure, that the writeup is intended for the board to boot into JTAG.  I'll need to head to the office to try this out.

- I'm still worried about starting with "Versal VCK190 Evaluation Platform" since I have an ES1 board.  I might need to repeat using the ES1 platform....

-Tom

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torid
Xilinx Employee
Xilinx Employee
484 Views
Registered: ‎08-01-2007

Hi Tom, All of these have been tested on the ES1 platforms, so you should be fine. I'll pass along the feedback on more specifically calling out to just build the AIE project.

florentw
Moderator
Moderator
408 Views
Registered: ‎11-09-2015

Hi @tdurand 

Please follow the tutorial on github.  The one on https://xilinx.github.io/ seems to be the initial release of the tutorial which has issues

Am not yet able to run the application (Step 4. Run the System).  I think, not sure, that the writeup is intended for the board to boot into JTAG.  I'll need to head to the office to try this out.

Booting using SD card should probably work as well. One thing I noticed this week is that the TCL file to build the platform in vivado is incorrect. It is not enabling the SDcard or UART controllers thus HW and HW emulation will not work if you created the design based on this. I need to fix the script and send a pull request.

Also if you are using the version from https://xilinx.github.io/ you will face the same issue

Maybe when Step 3 says "Change the Active build configuration to Hardware and rebuild the project", it meant to rebuild only the AIE project?

No for step 3 you should build the full system.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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