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cdr74
Visitor
Visitor
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Registered: ‎09-23-2019

FFT IP pipeline latency

Hello!

I am doing a research, and I would like to compare the calculation speed of the Xilinx FFT core to my DFT solution. If I understood it right, the IP generator (v9.1) gives the latency of the whole process, including loading and unloading the data into and from the core. Is there a way, to extract only the calculation latency (without the loading and unloading latency) of the core, to be able to do a fair comparison of calculation speed with my solution?

Thank you!

Peter

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@cdr74 ,

How are you defining latency?  The number of clock cycles from the first sample in to the last sample out would include loading and unloading.

Dan

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cdr74
Visitor
Visitor
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Registered: ‎09-23-2019

I would like to know the length of calculation itself. As in, in the case of this core, from the time the last sample is loaded, to the time the first output is ready to be unloaded.

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