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DH1990
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Registered: ‎11-05-2020

FFT bit inversion input

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In the test project, use the forward FFT to transform the signal from the time domain to the frequency domain, and then use the inverse FFT to transform the frequency domain signal back to the time domain. When both FFT and inv FFT adopt pipeline architecture and natural sequence output, it can be realized, as shown in the following figure (ifft_m_axis_data_tdata_M, ifft_m_axis_data_tdata_L are the imaginary part and real part of invFFT output respectively):

正确结果.png

Now the problem is, in order to save resources, I want to use FFT bit inversion output, and output data to inv FFT. According to page 6 of manual PG109, Burst I/O architecture uses DIT algorithm, so I set FFT to pipeline architecture, bit inverted output, and inv FFT is Radix-2 Burst I/O architecture, bit inverted output, but the output result is not correct, as shown below:

微信图片编辑_20201106095624.jpg错误结果.png

May I ask what went wrong?

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @DH1990 ,

Is the input to IFFT core in "Natural" order ? The input to the FFT IP should be in natural order. 

In your design, the output from the pipelined FFT is in bit-reversed order which needs to be converted to Natural order before applied to the IFFT core.

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vkanchan
Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎09-18-2018

Hi @DH1990 ,

Is the input to IFFT core in "Natural" order ? The input to the FFT IP should be in natural order. 

In your design, the output from the pipelined FFT is in bit-reversed order which needs to be converted to Natural order before applied to the IFFT core.

View solution in original post

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DH1990
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Registered: ‎11-05-2020

The input of IFFT is not in "Natural" order , but a bit inversion output from FFT.

If the input of IP core cannot  the bit-reversal sequence, how does DIT algorithm implement? How to understand the BURST IO architecture using the DIT algorithm,on page 6 of the manual PG109? Thank you.微信图片编辑_20201106095624.jpg

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vkanchan
Xilinx Employee
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Registered: ‎09-18-2018

Hi @DH1990 

The input to the core should be in natural order irrespective of architecture. THis is mentioned in PG109. Please see the below snapshot.fft_input.jpg

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DH1990
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Registered: ‎11-05-2020

I have seen this passage, but I just don’t understand the passage on page 6. OK. Thanks a lot.

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