12-04-2020 11:39 AM
I'm trying to configure a 4 channel, radix 2 FFT for selectable length(16K max), scaled and direction. According to the documentation, the bit field should be 124 bits wide- 5+3(pad) bits for size, 4 bits for direction and 4 groups of 28 bits for scaling for a total of 124 bits. This is what is shown in the IP-> implementation tab. However, the bit field width is 136 bits on the symbol tab!
If I write to the 124 bit field width as described, it doesn't work. I took a guess and padded the 4 bit direction by 12 bits to start the scale values after 12 padded bits. It appears to work. What should this be and why is the documentation wrong?
I can't look at the vhdl for the FFT as it is encrypted. The only thing that I can see is that it takes 136 bits down to 121 bits, which is the correct number of active bits with no padding. Did I win the lottery and guess where the missing bits should go? Why doesn't the IP core, documentation and implementation agree??
BTW, this is 2019.2 and FFT core 9.1
03-02-2021 06:34 PM
@danb2xilinx , this is a known issue, we will fix it in the next IP core release, as this is just a wiring issue, which does not impact FFT IP functionality or QOR, so, you can just ignore extra bits in the s_axis_config as a temporary work around. Hope it helps.
03-03-2021 06:13 PM
@danb2xilinx , I will also add that the additional bits will not lead to additional hardware because they will be removed during optimization in the implementation tools. We will publish AR# 76226 to Xilinx.com for this known issue.