10-22-2019 11:59 PM
I have followed the method in this thread (https://www.xilinx.com/support/answers/58582.html) to make a working block design for PYNQ-Z1 board (https://pynq.readthedocs.io/en/latest/getting_started/pynq_z1_setup.html) using xilinx FFT and AXI-DMA IPs. I added the necessary board files (https://github.com/cathalmccabe/pynq-z1_board_files/raw/master/pynq-z1.zip) to Vivado2015, changed the target of the existing example project and compiled the design for PYNQ-Z1 board. When I uploaded the bitstream and .hwh file on the board and ran the python program I got an error (screenshot attached). Can anyone help, please?
11-12-2019 02:28 AM - edited 11-12-2019 02:56 AM
I run the exact same configuration with FIR filter using Vivado 2019.1. And it is working fine. Then only difference, which I can see is in the files. I copied .bit and .tcl file with SAME NAME (e.g. fir1.tcl and fir1.bit file) instead of .hwh file.
The .tcl file is generated as below,
In Vivado, go to Export -> Export Block design -> save the .tcl file at desired location.
Can you try with .tcl file as well.
Also, plesae share the complete error.
What is the value of 'x1' in the Python code. May be you defined in some other shell in Jupyter notebook.
Since error is coming at dma.recvchannel.wait(), can you try to replace the '.wait()' with 'wait_async()' as below,
Further, give it a try without wait statement as well.
11-12-2019 10:24 AM
Thank you, @meherp . x1 is an array of 32-bit integer that I feed into the buffer. I found out that I had some issue in defining the integer size properly in declaring the buffer. changing that solve the problem on Z1 board.
However, I made a similar design for ZCU111 eval board (RFSoC). That seems to be giving the same error. I would try the wait_async() there. Thank you!