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vytautas
Explorer
Explorer
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Registered: ‎10-01-2007

FFT pcore in MB with FSL

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Hello, dear colleague.

Till this time I cannot find right solution for my (I have so though) simple project: FFT pcore generated with CoreGenerator implementation in MicroBlaze with FSL bus. Discussion this about was moved to EDK and Platform Studio section (lick here).

  1. I'm using 10.1.3 version of EDK.
  2. FFT pcore is generated with CoreGen and connected to MicroBlaze project with FSL bus.
  3. I wrote wrapper (see attached file) (gft.vhd).
  4. C application is listed bellow:

int i, val=34, res[20];
for(i=0; i<16;i++){

putfslx(val, 0, FSL_NONBLOCKING);
}
for(i=0; i<16;i++){
getfslx(res[i],1,FSL_NONBLOCKING);
printf("Result is: %d\n\r", res[i]);
}

 

I write 16 input words and then read 16 words. Hyper Terminal prints 16 times Result is 0.

Maybe wrapper is wrong, maybe FSL_CONTROL signal should be send, maybe reset is not given? Please advice me

Message Edited by vytautas on 08-10-2009 07:15 PM
Message Edited by vytautas on 08-14-2009 09:49 AM
Best Regards,
Vytautas
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vytautas
Explorer
Explorer
11,431 Views
Registered: ‎10-01-2007

Hello.

This problem looks like was solved by changing initial values of XN_RE, fwd_inv, fwd_inv_we inputs. They was changed to zero. FFT pcore gives results in first time of calculation during simulation and in EDK project.

Best Regards,
Vytautas

View solution in original post

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vytautas
Explorer
Explorer
11,130 Views
Registered: ‎10-01-2007

Hello, again.

Some changes I have done on this project. Now I will post simulations results of FFT core. Don't understand - it's bug of FFT or its my personal bug, but simulation results are very strange. In diagram bellow is simulation done with ModelSim. Very strange is point 3, where result written from FFT to FSL_M_Data is allways the same: 0xF777777.

After second time of full operations result is more real.

Similar discussion could be find here:

http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=10503&jump=true#M10503

Thank you for help!

Best Regards,
Vytautas
FFT_diagram3.JPG
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vytautas
Explorer
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Registered: ‎10-01-2007

Hello.

Please advice whether this is related to the pcore bug?

Because I have no more idea, don't know how to test it to get correct results, nots just 0xF777777...

Thanks

Best Regards,
Vytautas
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ywu
Xilinx Employee
Xilinx Employee
11,105 Views
Registered: ‎11-28-2007

The waveform doesn't seem to match your code as the input to fft (xn_re) on the waveform is 32-bit but it's 16-bit in the code.

 

Cheers,

Jim

 

Cheers,
Jim
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vytautas
Explorer
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11,094 Views
Registered: ‎10-01-2007

Hello.

yes you are right, code attached in first post doesn't match waveform in picture. I will send my last code - FFT with Floating point. By selecting floating point CoreGen automatically selects 32-bit as inputs and outputs

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
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Registered: ‎10-01-2007

This is my code  regarding to diagram

FFT 32-bit Floating Point, NFFT=00100

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
11,080 Views
Registered: ‎10-01-2007

I can attache full ISE project to see this issue.

Really first output is very strange.

Also, if I use EDK (by giving float point values) I get result incorrect too.

Best Regards,
Vytautas
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ywu
Xilinx Employee
Xilinx Employee
11,079 Views
Registered: ‎11-28-2007

It will be really helpful if you can attach your full ISE project.

 

Cheers,

Jim

 

Cheers,
Jim
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vytautas
Explorer
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Registered: ‎10-01-2007
I have attached full project
Message Edited by vytautas on 08-24-2009 11:35 PM
Best Regards,
Vytautas
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vytautas
Explorer
Explorer
11,432 Views
Registered: ‎10-01-2007

Hello.

This problem looks like was solved by changing initial values of XN_RE, fwd_inv, fwd_inv_we inputs. They was changed to zero. FFT pcore gives results in first time of calculation during simulation and in EDK project.

Best Regards,
Vytautas

View solution in original post

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vytautas
Explorer
Explorer
8,366 Views
Registered: ‎10-01-2007

Hello.

Does anybody has correct Finite State Mashine for FFT pcore?  I use one wrapper, but cannot find problem in code: this code reads two times the same input from FSL.

Please find attached file.  I have taken this project and did some modifications, because really it doesn't works at all:

http://www.eecg.toronto.edu/~pc/courses/432/2005/projects/midi.pdf

Problematic are states ragarding to reading of inputs. 3 clock delay should be between every reading, but actually this codes handles by fallowing:

input_values = {1.0, 2.0, 3.0... } (16 numbers at all)

fft gets [1.0, 2.0, 2.0, 3.0, 3.0....]

First number was read one time, next values - two times. 3 months I try to solve this issue and without results :(

Please help me

Best Regards,

Vytautas

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
8,347 Views
Registered: ‎10-01-2007

Hello.

I did several changes in FFT wrapper file. Now FFT pcore reads such inputs:

[IN(0),IN(1),IN(2),IN(3),IN(4),......,..IN(13),IN(13),IN(13),]

It's very hard to understand something from ModelSim if I dont know how exaclty handles FSL bus, how does it sets FSL_S_EXISTS signal...

Please take a loot at attached wrapper. I dont know any idea, how to fix it.

There are problems regarding maybe to CE signal,required delays or read_data state...

Best Regards,

Vytautas

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
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Registered: ‎10-01-2007

Hello.

In attached file is full design with this little mistake

Best Regards,
Vytautas
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ywu
Xilinx Employee
Xilinx Employee
8,326 Views
Registered: ‎11-28-2007

Why do use set ce to 0 in Read_Inputs state?

 

 

            when Read_Inputs =>
                ce <= '0';
                if (FSL_S_EXISTS = '1') then -- If data exists

 

Cheers,

Jim

 

Cheers,
Jim
vytautas
Explorer
Explorer
8,320 Views
Registered: ‎10-01-2007

Hello Jim.

You are pretty right, by setting CE in the state Read_Inputs makes logic strange, but please look how it handles at all.

  1. In the state Idle if FSL_S_Exists is 1 and 15 inputs are not read, by second clock CE changes to 1, and state changes to Read_input
  2. In the state Read_inputs if FSL_S_Exists is 1 and 15 inputs are not read, by second clock CE changes to 0, state changes to Idle, and so on...
  3. so, if I need to read data to the buffer dataInBuf (Idle state), FFT should not work, so that in the state Idle I have CE=0;  
    but if I need to put data from buffer dataInBuf to FFT XN_RE (Read_inputs state), CE=1.
  4. Therefore I set CE=0 in state "Read_inputs".
  5. I wrote additional one more state "Waiting". I use it in the case if I have read 15 number of inputs and need to go to the sate End_Of_Read. But clock is set to 0 in state Read_inputs, so that state Waiting changes CE to 1, because last input should be read.
  6. It's somewhere here misstake. 15th input is reading two times. :(.(I attached file)

Best regards,

Vytautas

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
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Registered: ‎10-01-2007
Cool, I found the issue. This code works well.
Best Regards,
Vytautas
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vytautas
Explorer
Explorer
8,315 Views
Registered: ‎10-01-2007

Hello again.

I have one more question about FFT project. My FFT project works very well if nfft is 16 points. C application puts and gets correct 16 float numbers. 

If I set nfft to 256 points, C application puts all 256 values, FFT calculates them correct, but reading back  first value fsl_isinvalid(invalid) function sets  invalid to 1, reading next values all is ok!. Then function microblaze_nbread_data_fsl(out[i], 1) sets variable out[i]  to first zero, then to 1th, 2th...values and two times 255th values of FFT output...

Best Regards,

Vytautas

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
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Registered: ‎10-01-2007

Hello.

I have done several tests with FFT pcore. And only one version works well - if NFFT is 16!

If NFFT is higher than 16, reading first value of output fsl_isinvalid  gives error!

Does it is related to buffer overflow?

DoI need additional delay (counter)?

Does it's related C application?

 

Please help to isolate this bug...

Thank you!!!

Best Regards,
Vytautas
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vytautas
Explorer
Explorer
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Registered: ‎10-01-2007

Hello.

Finally my FFT core works per FSL. Several magic code lines have solved it. FFT calculates 256 number of float inputs. Result is well.

But if I repeat calculation second time (without resetting FPGA), FFT takes 3 first values as zero and doesn't read last 3 values...

My VHDL code resets all components after calculation and goes to initial state.

Does it is possible that FSL FIFO  contains some zeros?? How could I reset FSL fifos?

Thank you

Best Regards,
Vytautas
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