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7,709 Views
Registered: ‎09-16-2007

FFT v3_2 HDL code generation error

Hi,
I am using FFT v3_2 block in the System Generator 9.1 (block v4_1 cannot be supported) and after generation of the HDL code, the code compiler within ISE 9.1i foundation reports an error in design at the following line.
 
It is at the begining of the entity declaration for FFT block and the error is that the library is not found:
"
library UNISIM;
...
use UNISIM.VPKG.all;
 
"
 
The "VPKG" part is not recognized by the HDL compiler.
Does anyone knows what is this about?
 
I have just included everything within the UNISIM library to pass this, how big error did I make?
 
Thanks in advance.
 
Regards,
Miloss
 
 
 
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Xilinx Employee
Xilinx Employee
7,699 Views
Registered: ‎08-07-2007

There are no known issues with synthesizing a System Generator design with any of the FFT blocks.  Please open a webcase with Xilinx support to investigate the errors you're seeing.

http://www.xilinx.com/support/clearexpress/websupport.htm
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7,363 Views
Registered: ‎03-13-2008

hi,
i am also facing the same problem when running ..........pls help me how can i solve this proble............

Thanks
surendra
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