06-28-2018 09:30 AM
I am currently porting a Virtex-5 ISE design to Zynq7045 on Vivado.
My existing ISE design is using FFT 7.1, now I have to move to FFT 9.0.
The input data to the FFT is coming from an ADC which delivers the data and the CLK to the FPGA, the clock from the ADC is also clocking the FFT. With FFT 7.1 this is running fine, using Pipelined-Streaming mode, I can always sample one full frame coming from the ADC without interruption.
Now PG109 for FFT 9.0 states in several places, that the s_axis_data_tready signal needs to be obeyed at the input, and it may go low while loading one frame (PG109, Oct 4, 2017, p.41, p. 50, p.89, p.91).
My question is, does this really also hold true for Pipelined-Streaming mode, w/o cyclic prefix, unscaled? This would be a major problem, because I definitely need to work on consecutive samples from the ADC, skipping samples would render the result useless.
I cannot really believe that the FFT core was degraded so seriously, can anyone comment on that?
07-05-2018 02:52 AM
FFT v9.0 function is not changed, it's the same with v7.1, it is just add the AXI-interface wrapper around the previous FFT core. So you should be able to get v9.0 working the same way with v7.1.
07-18-2018 01:52 AM
Is it possible to get an official statement from Xilinx that it is indeed possible to use the FFT 9.0 core without interruption, even though the documentation says otherwise? My whole design would rely on this, and "you should be able" is a little weak for that.