06-26-2013 05:51 AM
Here is my current design situation:
I am designing an FPGA to down-sample a 160MHz input signal to 51.2MHz using the fixed-fractional rate decimator in the FIR compiler. This requires interpolation by 8, filtering, and decimation by 25. The process has been simulated in Matlab with the upfirdn() function and by designing a lowpass filter being sampled at 8*160MHz = 1.28GHz.
My question is this:
For the FIR compiler in fixed-fractional rate down-sampling mode, should the filter coefficients be designed at the input sampling rate (160MHz) or post-upsample rate (1.28GHz)? I didn't find clear wording in the data sheet to help me understand the correct filter design, but I'm assuming the filter coefficients should be provided with respect to the input sampling rate.
06-26-2013 09:14 AM
Disclosure: I've never used any of the Xilinx FIR tools/models. (I have designed multi-rate filters using Xilnx FPGAs).
You design your low-pass filter at the interpolated rate (for you 1.28 GHz). I can't see how the Xilinx software could do this for you. Specifying the filter at the input sample rate makes no sense.
One assumes the Xilinx FIR compiler does the polyphase filtering implementation correctly.
07-26-2019 05:36 AM
the filter place between upsampler and down sampler. so you should deign filter coeffcients for 1.28Ghz.
( Dear Newbie,
I have understood the theory concept of Fractional decimation rate converter. but i am unable to use FIR IP, so can u help me.
For the mentioned (Yours specification) parameters, I have configued FIR IP, The filter speciofication i got it, but the Hardware oversampling specifications I did not get till now. So can you tell what values i should fill in those areas. Please do not forget to reply.)