01-08-2020 06:30 PM
I have configured the FIR Compiler for an 11 tap FIR decimating 2:1. The input clock rate is 1/4 the sample rate so 4 samples are applied to the input every clock cycle (Super Sample Rate is 4). The coefficients are symmetrical. Input data and coefficients are both 16 bits.
I expected ((4 samples/clk * 11 Taps)/2 symmetric coefficients/2 decimation) or 11 multiplers.
The actual number of multiplers is 22 which leads me to believe there is no resource reuse based on the decimation rate. Is there a way to configure the FIR Complier to realize a resource reduction based on the decimation factor?
01-09-2020 11:21 AM
Some additional information.
I built the same FIR but set the input sample period = 1. The result was a FIR that used only 3 multipliers, which is what I would expect roundup(11taps/2 symmetry/2 decimation). It appears that when the FIR is operating with an input sample period that is a fraction (1/4) of the clock period, configuring the filter for decimation will not improve the resource reuse. Is this a known deficiency for the SSR version of the FIR?