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shaikon
Voyager
Voyager
901 Views
Registered: ‎04-12-2012

FIR Compiler Configuration

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Hello,

My system has 9 ADCs sending information at a 80 MHz rate.
I want to use the FIR Compiler IP core to filter the data from all channels.
https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf

My processing clock domain is 250 MHz and in order to use less DSP blocks, I want to take advantage of the fact that the processing clock is higher then the effective data rate ( 80 MHz )
I have 2 questions :

1. I specified the "Input Sampling Frequency" to 80 MHz and the Clock Frequency to 250 MHz. Does this mean that the average rate of the AXI Stream Valid signal mustn't exceed 80,000,000 per second ?
2. From reading the FIR Compiler's documentation I understand that the fact that I have 9 ADCs should be expressed in the "Number of Paths" field ( page 79 ) and not "Number of Channels" ?

 

FIR_Compiler_Configuration.JPG
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vkanchan
Xilinx Employee
Xilinx Employee
728 Views
Registered: ‎09-18-2018

Yes, it is a valid configuration in FIR which will work

View solution in original post

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vkanchan
Xilinx Employee
Xilinx Employee
833 Views
Registered: ‎09-18-2018

Hi @shaikon ,

For point 1 : Yes , the input data TVALID signal should be used to maintain the sample rate of 80MHz at an average.

Point 2 : Number of Data paths means the data path of the filter is replicated for each path, while specifying  number of channels indicates that a single data path is shared in a TDM fashion among the number of channels running at a lower rate.

Given input rate of 80MHz and clock of 250 MHz, atmost 3 channels can be multiplexed on a data-path.

since there are 9 channels in design, 9 parallel data paths can be used each running at 80MHz, (OR) 3 parallel data paths can be used, with each data path, running at 250MHz is multiplexed between 3 channels of 80MHz each.

shaikon
Voyager
Voyager
813 Views
Registered: ‎04-12-2012

since there are 9 channels in design, 9 parallel data paths can be used each running at 80MHz, (OR) 3 parallel data paths can be used, with each data path, running at 250MHz is multiplexed between 3 channels of 80MHz each.

What are the benefits of using the Red solution vs the Green ?


 

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vkanchan
Xilinx Employee
Xilinx Employee
780 Views
Registered: ‎09-18-2018

Hi @shaikon ,

Depending on the coefficients and symmetry , the red one might use lesser resources, at the same time being more complex to handle than green

The below configuration is with an assumption that single rate filter. Red configuration might not be possible for rate change filters.

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shaikon
Voyager
Voyager
752 Views
Registered: ‎04-12-2012

My filter does have symmetric coefficients...

Based on your explanation (I want to make sure that I got it right) - this is how I thought about implementing it:

1. I have 9 separate ADC channels sending data synchronous to the same 80 MHz clock (data is valid all the time).

2. I'll use an asynchronous FIFO and transfer it to the 250 MHz (filter clock domain). With every read from the FIFO I'll issue an AXI Stream Valid towards the filter.

3. Number of Channels = 1 , Number of Paths = 9.

4. Input Sampling Frequency = 80 MHz , Clock Frequency = 250 MHz.

Will this solution work ? Do you suggest something different ?

 

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vkanchan
Xilinx Employee
Xilinx Employee
729 Views
Registered: ‎09-18-2018

Yes, it is a valid configuration in FIR which will work

View solution in original post