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thejashree_13
Adventurer
Adventurer
398 Views
Registered: ‎07-29-2019

FIR Compiler IP Channel configuration

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Hello,

We are planning to use FIR Compiler IP in our design and I have questions on the same.

We have a 8 bit ADC running at 250Mhz in DDR rate. So I will be having 16 bit of ADC data in FPGA which is running at 250MHz(SDR, after conversion). So the FIR compiler should run at 500MHz. Since running FIR at 500MHz is difficult for our design timing constraints we just wanted to understand the channel configuration of the FIR filter. 

If I configure the FIR Compiler to use 2 parallel data channel where one channel will take 8 bit data and the other channel will take the 8 bit data, then I can configure the FIR filter to 250MHz. 

So I just wanted to understand whether these parallel data channel will have separate path with all the constraints for the two channels being same(both channel having single coefficient set)?.
So on the output side we have separate response for each channel. Please confirm my understanding since I am new to FIR concepts.
I kindly request you to provide the response for the same.

With regards,
Thejashree

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nathanx
Moderator
Moderator
344 Views
Registered: ‎08-01-2007

Yes, your understanding is correct, the Parallel Data Channel Filters allow user to process multiple parallel datapaths with the same
filter coefficients. In this configuration, the FIR Compiler can share control logic and coefficient memory resources between the parallel datapaths. The screenshot below shows the data input and output channel which consists of two data paths.

nathanx_0-1627539985451.png

 

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nathanx
Moderator
Moderator
345 Views
Registered: ‎08-01-2007

Yes, your understanding is correct, the Parallel Data Channel Filters allow user to process multiple parallel datapaths with the same
filter coefficients. In this configuration, the FIR Compiler can share control logic and coefficient memory resources between the parallel datapaths. The screenshot below shows the data input and output channel which consists of two data paths.

nathanx_0-1627539985451.png

 

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lvalena
Xilinx Employee
Xilinx Employee
336 Views
Registered: ‎12-09-2015

\(^^)

Maybe check the "Super Sample Rate" feature described in PG149?

lvalena_0-1627542441770.png

 

 

thejashree_13
Adventurer
Adventurer
289 Views
Registered: ‎07-29-2019

Hi @lvalena and @nathanx ,

Thank you for response provided. 

With regards,
Thejashree

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