01-10-2019 11:53 AM
I am attempting to generate a 512-tap FIR filter that uses only 256 DSP slices.
With my input samples coming in at 250 MHz, this means that I need to supply a 500 MHz clock to the FIR module.
My input samples are coming from an AXI Stream Broadcaster clocked at 250 MHz and the FIR Output goes to a module clocked at 250 MHz.
What is the best way to handle the clock domain crossings between input and output? Would a simple AXI Stream Clock Converter work? Should I use a AXI Stream Data FIFO?
01-13-2019 08:04 PM
From your description, the input samples are provided to the core at 250MHz. The filter is clocked at 500 MHz.
The FIR compiler is by default a single rate filter i.e Input sample rate is equal to output sample rate. Since the input sample rate is 250 MHz, the core will also produce the output at 250 MHz,
The clock frequency of 500 MHz to core allows the core 2 clock cycles for every 1 input sample. This forms the Hardware oversampling specification to the core as 2. The core uses this extra clock cycle for computations using lesser DSP Slices. Hence the lesser number of DSP slices.
The output samples are produced by the core and are validated using the m_axis_data_tvalid signal at the output of the core. This signal along with m_axis_tdata can be used to directly feed the downstream module at 250 MHz.
The FIR compiler core has to be configured by specifying the input sample period and clock frequency in the channel specification tab through Vivado or specify the hardware oversampling as 2 in the System Generator core.
01-13-2019 08:11 PM
Thanks for the response. Yes, I agree with your reply, however my question more specifically centered around the AXI infrastructure needed to connect upstream and downstream logic.
As it stands, the project throws an error when I try to simply connect the upstream block and the downstream block (both clocked at 250 MHz) to the FIR filter (clocked at 500 MHz) - the error being that clock domains and clock frequencies do not match.
Could you comment on how to resolve this interfacing problem?
01-15-2019 02:47 AM
Is this a system generator design or a Vivado design ? can you please share the design files for me to take a look at ?