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Visitor
Visitor
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Registered: ‎05-15-2019

FIR Compiler Question: how to control the 'unit delay'?

Hello,

I have been implementing a few different DSP systems on a Xilinx Kintex-7 using verilog code, system generator and/or a combination of both. 

I can not get the FIR IP core to produce my desired output because I am unsure how to properly control the speed of the 'unit delays'. As of right now, all I have done is loaded my coefficients and compiled. This would mean that each unit delay/zero order hold/register  (or whatever you want to call it!)  in the chain of the FIR

https://en.wikipedia.org/wiki/Finite_impulse_response#/media/File:FIR_Filter.svg

is based on the system clk speed (245.76 MHz). Of course, I need the delays to be based on the actual ADC rate  e.g. 5MHz. I do the down sampling manually before I input this signal into the FIR filter. I do this using registers and a counter to get an output as  245.76MHz / n  where I control n. I set n depending on the project, but usually it's around n=25-50 which gives sample rates varying between  ~5-10 MHz.

 

I see many potentially relevant settings with the FIR compiler and I have read another thread but it did not help as this person was talking about something slightly different.  There is 'Hardware Oversampling Specification' where I tried "Format: Input sample period",  "Sample period:  n"  and it did not work. Also, there is control options and a CLKEN.

Can anyone please help me? 

A tldr version of my question: Given that I want to pass a signal sampled at 5 MHz through a FIR filter and my clock speed is 245.76 MHz, how do I configure the FIR IP core in System Generator to make each delay in the FIR  (i.e. time between moving data through buffer) correspond with  T_d=1/5MHz  not  T_d=1/245.76MHz?

 

Thank you 

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Moderator
Moderator
455 Views
Registered: ‎08-01-2007

Since your clock speed is 245.76 MHz, the delay of one clock cycle is 1/(245.76 MHz), so to get delay of (1/5MHz), you can use with multiple clock cycles.

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Visitor
Visitor
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Registered: ‎05-15-2019

Hello, thank you for the reply

 

I understand the concept, I have programmed my own IIRs and have done register buffer with a counter so that I can get the feedback in my IIR to match my input rate. My question comes from the fact that I am planning to do a very large FIR, so I want to use the Xilinx IP core as it's very efficient.

 

With respct to the Xilinx FIR compiler, which settings should I use?  I've read the FIR compiler pdf and am still left confused about what to do  as what I tried did not work

 

 

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Registered: ‎06-21-2017

If you are using the FIR compiler, you need to work within the boundaries of the AXI stream.  Design your filter for a system clock rate of 246 MHz and an input rate of your fastest rate, say 10MHz.  Use your clock divider/sample decimator to produce a tvalid signal for the input of the FIR.  The tvalid on the output will tell you when a filtered sample is ready. 

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