UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant vizziee
Participant
5,704 Views
Registered: ‎10-21-2009

FIR Compiler problem: Output channels getting swapped

Jump to solution

Hello,

 

I am facing this peculiar problem with the FIR compiler v 5.0 (ISE 11.2, Virtex SXT95). I am implementing a 6-channel decimation-by-5 FIR filter using this core. The outputsare get decimated as expected. However, in every cycle, the outputs get swapped in the sequence and appear on different channels (in the functional simulation in ModelSim XE 6.4b). I rely on chan_out signal to separate the outputs and the sequence is different in every cycle.

 

While debugging this design, I performed the following checks:

 

- I checked my input stream to see if the channels get swapped at the input stage itself. But they don't.

- I checked if the nd signal is any way different in the other cycles. It is same.

 

Has anyone encountered the similar problem?

 

Regards,

Kumar Vijay Mishra.

0 Kudos
1 Solution

Accepted Solutions
Participant vizziee
Participant
6,412 Views
Registered: ‎10-21-2009

Re: FIR Compiler problem: Output channels getting swapped

Jump to solution

I resolved the problem of outputs getting clipped. Turns out I was using SCLR (deterministic behavior) option for the FIR core. When this happens, the core forces output to be zero initially till it flushes out the internal values. Some portion of my valid input was in this time period and hence its corresponding output was forced to zero. I delayed my input and could then see the full output.

 

Regards,

 

Kumar Vijay Mishra.

0 Kudos
2 Replies
Participant vizziee
Participant
5,698 Views
Registered: ‎10-21-2009

Re: FIR Compiler problem: Output channels getting swapped

Jump to solution

Turns out I was not properly resetting the core in every cycle. After fixing this bug, the channels are in the expected order. However, the initial part of the channels gets clipped. Any clue? Should I pad the inputs with zeros in the beginning?

 

Regards,

 

Kumar Vijay Mishra.

0 Kudos
Participant vizziee
Participant
6,413 Views
Registered: ‎10-21-2009

Re: FIR Compiler problem: Output channels getting swapped

Jump to solution

I resolved the problem of outputs getting clipped. Turns out I was using SCLR (deterministic behavior) option for the FIR core. When this happens, the core forces output to be zero initially till it flushes out the internal values. Some portion of my valid input was in this time period and hence its corresponding output was forced to zero. I delayed my input and could then see the full output.

 

Regards,

 

Kumar Vijay Mishra.

0 Kudos