FIR Core giving Wrong output in Digital Down Convertor design
I am designing a Digital Down converter.First Block is an Mixer ,implemented using an Xilinx DDS core ,Second Stage a low pass filter using FIR compiler ,3rd stage is an LPF decimate by 4 decimator implemented using FIR and forth stage is decimate by 10 LPF FIR compiler.Data is coming from ADC and Output is fed back to DAC for verification.
My first three stages giving right o/p (i.e. output of Mixer ,1st Anti aliasing LPF,Decimate by 4 filter is as expected).
However 4th stage DECIMATE BY 10 LPF FIR Decimator output is some fixed garbage value which changes bitfile to bit file.
I have configured all FIR core(stage 2 ,3 and 4) in a similar way.then Why 4th stage is not giving output is a issue.
system clock= adc clock= DAC clock=84MHz.
IF INPUT AT adc=12 MHz
output data frequency after 1st decimation=84/4=21 Mhz
expected o/p data frequency after 1st decimation=21/10=2.1 MHz
4th stage o/p is visible in Questsim simulation however in FPGA o/p is not there.