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Visitor
Visitor
648 Views
Registered: ‎03-19-2019

FIR Filters not working

I have a DDS with a clock frequency of 250 MHz and a phase width of 48 bits generating two 16 bit sinusoids.  A highpass filter is used to filter the top 16 bit of the 32-bit word output which corresponds to sine, and a lowpass filter is used to filter the bottom 16 bits of the output corresponding to a cosine.  The highpass filter has a cutoff frequency of .7pi rads/sec with a sampling rate of 250 MHz and the lowpass has a cutoff frequency of .1pi rads/sec with the same sampling frequency. Neither of the filters is working appropriately.  The lowpass filter does not attenuate as I increase the frequency of the DDS, and the highpass filter adds strange artifacts in the low frequencies that resemble the transient response of a highpass filter.  This is all done in LabVIEW 2017.  Any idea on how I could go about troubleshooting this?  I am new to the XILINX.

Thank you,

Sergio 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @laraser15 ,

Can you please share the filter design parameters and the FIR compiler block to check the configuration.

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Visitor
Visitor
551 Views
Registered: ‎03-19-2019

Hi @vkanchan,

I apologized for that.  Attached is a zip file containing the configurations of the lowpass and highpass filters including the coefficient files.  There are too many images to be inserted within the text.  

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Xilinx Employee
Xilinx Employee
534 Views
Registered: ‎09-18-2018

Hi @laraser15 ,

I checked the FIR compiler IP configuration. In the HPF, the input sampling frequncy is 250MHZ and clock frequncy is 250MHz. This means that a valid input sample is presented to the core every clock cycle.

Can you please confirm if the valid input samples are being provided to the core ? 

The LPF has an input sampling frquency of 125MHz. The input samples are valid for every 2 clock cycles. 

Are you using a single DDS to generate both the sine and cosine ? If so are you using any other block to change the sampling rate of sine and cosine before it goes into the FIR cores.

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Visitor
Visitor
512 Views
Registered: ‎03-19-2019

Hi @vkanchan,

A single DDS is being used to generate both, the sine and cosine.  No decimation is being currently being done.  The DDS and both FIR filters are placed inside a single-cycle timed loop clocked at 80 MHz.  Can this be the reason why the filters are not behaving appropriately?  The DDS is clocked at 250 MHz, but the loops are only getting samples at 80MHz.  I assumed that the DDS would run freely, outputting samples at 250 MHz regardless of the SCTL. 

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Xilinx Employee
Xilinx Employee
482 Views
Registered: ‎09-18-2018

Hi @laraser15 ,

The clock frequency specified in the DDS core as well as the FIR filter is the frequency with which it is going to operate. Please see the definition of the system clock in the PG141. It states it is the frequency at which the core is clocked.

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