01-05-2021 10:38 PM - edited 01-06-2021 06:56 AM
I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples) and to reach valid data continuity in the output. However, there is problem with the input. The IP expects valid data in each 1 clock cycle and gives valid output data in every clock cycle. I use an Asynchronous Fifo to change 20MHz to 20.48MHz in the input. In some cases the Fifo can't supply valid data to the input as expected and s_axis_tready is always high. So, this situtation breaks valid data continuity at the output port. How can I solve this problem ?
Filter Options and Channel Spesifications
Filter Type --> Interpolation
Rate Change Type --> Fixed Fractional
Interpolation Rate Value --> 128
Decimation Rate Value --> 125
Input Sampling Frequency --> 20MHz
Clock Frequency --> 20.48MHz
Clock Cycles Per Input --> 1 !!(How can I supply with 20 MHz ? The main clock is 20.48Mhz, and s_axis_tready is always high.)
Clock Cycles Per Output --> 1
01-06-2021 06:39 AM
You use s_axis_data_tvalid to indicate valid data (which will be mostly high, invalid, as you probably know 3 of 128 cycles) at the input. With the clock freq of 20.48 it should be fine although I haven't used Fir Compiler with these I/D rates.
You should have the AFIFO at the input, not output, to bring the 20 Msample / sec data to the 20.48 MHz domain.
You're output should be continuous at 20.48 MHz, one sample per clk.
01-06-2021 06:51 AM
There is already an AFIFO in the input, but I added prog full port to see FIR IP internal FIFO full. Then, I can see now s_axis_tready goes 0 now. However, the data in AFIFO slowly decreases by time and I am sure it will be empty after a time and output will be discontinuous due to there is no data at AFIFO. The main problem is bring 20Msample / sec with 20.48MHz domain. Because, samples are produced with 20MHz clock and IP expects valid data in each clock cycle in 20.48MHz domain.
01-06-2021 07:05 AM
You may need to use a dual clock FIFO. All you need to do is to make sure your FIFO doesn't go empty. And you may want to keep a minimum data on it as well.
01-06-2021 07:14 AM
I used a 1K AFIFO and there is a prog full signal on it which is triggered by 512 data. After prog full is triggered, valid data transfer starts to the ip. Also, Read clock is 20.48 MHz and Write Clock is 20MHz. But after a time prog full is not triggered and rd_data_count on the ip decreases by time.
01-06-2021 07:30 AM
From my experience (with audio, requiring continuous, real time data), if you need to produce 2048 samples every 100 usec (20.48 MHz) and you only receive 2000 in that time (20 MHz), you need a higher speed process that takes those 2000 values, generates the required 2048 and writes them to a buffer ideally at a higher frequency.
01-06-2021 09:52 PM
I can see the problem, and that is my question actually. How can I do that without a higher speed process to take 2000 samples to generate 2048 samples ?
01-07-2021 12:37 AM - edited 01-07-2021 12:57 AM
I would say it's impossible. 20 MHz inside an FPGA is nothing, what prevents you from processing data at 50, 100 MHz?
The problem is not the number of samples but the number of cycles/ periods. The only way I can see to produce more than 2000 samples in 2000 cycles is by creating more than one per cycle, which is in theory possible but you won't be able to send them to a FIFO in the same clock cycle.
01-10-2021 06:47 PM
The IP does not expect valid data on each clock cycle in a 20.48 MHz domain. That's why I mention using TVALID. I've done this before for very low duty cycle (and low duty cycle multichannel) filters.
Should be fine. Simulate it.